# Electrical Technology Grade 12 NSC November 2019 Memo (Eng) > Grade 12 Electrical Technology memorandum from the NSC November Exam 2019 (English), 16 pages. Read online or download the free PDF. - Page: https://www.hlayiso.com/library/electrical-technology-nov-2019-digital-memo-eng/e9814dad-e754-4203-9839-e8762979dbfa - Updated: 2026-09-27 - Subject: Electrical Technology - Grade: Grade 12 - Document type: Memorandum - Year: 2019 - Exam period: NSC November Exam - Curriculum: CAPS - Pages: 16 Breadcrumbs: [Home](https://www.hlayiso.com/) › [Library](https://www.hlayiso.com/library) › [Grade 12](https://www.hlayiso.com/library/grade-12) › [Electrical Technology](https://www.hlayiso.com/library/grade-12/electrical-technology) › [Electrical Technology Grade 12 NSC November 2019 Memo (Eng)](https://www.hlayiso.com/library/electrical-technology-nov-2019-digital-memo-eng/e9814dad-e754-4203-9839-e8762979dbfa) ## About this document Electrical Technology · Grade 12 · NSC November Exam · 2019. Memorandum, 16 pages. Read online or download the PDF. Read it free online on the page above; download the PDF from there. ## Document text Text extracted from the PDF. Layout, diagrams and tables may not survive extraction. ### Page 1 Downloaded from hlayiso.com Electrical Technology: Digital 1 DBE/November 2019 NSC – Marking Guidelines GRAAD 12 NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: DIGITAL NOVEMBER 2019 MARKING GUIDELINES MARKS: 200 These marking guidelines consist of 16 pages. Copyright reserved ### Page 2 Downloaded from hlayiso.com Electrical Technology: Digital 2 DBE/November 2019 NSC – Marking Guidelines INSTRUCTIONS TO THE MARKERS 1. All questions with multiple answers imply that any relevant, acceptable answer should be considered. 2. Calculations: 2.1 All calculations must show the formulae. 2.2 Substitution of values must be done correctly. 2.3 All answers MUST contain the correct unit to be considered. 2.4 Alternative methods must be considered, provided that the correct answer is obtained. 2.5 Where an incorrect answer could be carried over to the next step, the first answer will be deemed incorrect. However, should the incorrect answer be carried over correctly, the marker has to re- calculate the values, using the incorrect answer from the first calculation. If correctly used, the candidate should receive the full marks for subsequent calculations. 2.6 Markers should consider when and where a candidate has rounded off in a calculation, as well as the subsequent effect it has on the final answer obtained. The calculation should therefore be awarded marks on merit. 3. These marking guidelines are only a guide with model answers. Alternative interpretations must be considered and marked on merit. However, this principle should be applied consistently throughout the marking session at ALL marking centres. Copyright reserved ### Page 3 Downloaded from hlayiso.com Electrical Technology: Digital 3 DBE/November 2019 NSC – Marking Guidelines QUESTION 1: OCCUPATIONAL HEALTH AND SAFETY 1.1 • An employee with a sense of teamwork helps a team to meet its goals. ü • Teamwork helps a team deliver quality work. ü • Teamwork can win the respect of your co-workers. • Working together as a team can improve discipline in the workshop. • Teamwork will lead to improved productivity. (2) 1.2 1.2.1 The purpose of the Act is to: • Provide for health and safety of persons at work. ü • Protect against hazards arising from the activities of other people at work. ü • Establish an advisory council for occupational health and safety and related matters. • Provide for health and safety for persons in connection with the use of plant and machinery (2) 1.2.2 Workplace can be defined as any premises or place where a person performs work ü during the time of his employment. ü (2) 1.3 1.3.1 Employee. ü Learner, Supervisor, Team leader, Safety representative (1) 1.3.2 Health and safety representative. ü Inspector. (1) 1.4 • Remain calm. ü • Stop whatever you are doing. ü • Switch off machinery. • Notify a responsible adult or teacher. • If there is an emergency stop nearby activate it if necessary. • Move in an orderly manner to the nearest assembly point. NOTE: Procedure can be listed in any order (2) [10] Copyright reserved ### Page 4 Downloaded from hlayiso.com Electrical Technology: Digital 4 DBE/November 2019 NSC – Marking Guidelines QUESTION 2: SWITCHING CIRCUITS (GENERIC) 2.1 2.1.1 A – Bistable multivibrator ü B – Monostable multivibrator ü (2) 2.1.2 ü +V 0 t ü -V 2 marks = 1 mark for each correct half cycle If waveform is correctly drawn but inverted, 2 marks will be awarded NOTE: Due to the +V instead of -V typo on the answer sheet, the following responses are also accepted. (2) +V +V +V ü ü ü ü ü ü 0 0 0 2.2 2.2.1 Resistors R 1 and R 2 are pull-up resistors. ü ü Resistors R 1 and R 2 will hold both trigger pin 2 and reset pin 4 high. (2) 2.2.2 Trigger pin 2 will be pulled low ü and cause the IC output to 'flip' and rise high ü turning the LED on ü When set switch S 1 is pressed, (3) 2.2.3 Threshold pin 6 is purposely held at 0 V ü causing the IC not to reset, ü keeping the output high ü when S 1 is pressed. (3) 2.3 2.3.1 The output signal represents an inverting Schmitt trigger ü because the output signal is inverted ü with reference to the input signal. ü OR The output signal is at -V CC when triggered by the upper trigger voltage and swings to +V CC when triggered by the lower trigger voltage. (3) Copyright reserved ### Page 5 Downloaded from hlayiso.com Electrical Technology: Digital 5 DBE/November 2019 NSC – Marking Guidelines 2.3.2 ü ü + VCC VIN ü ü VOUT ü RF ü -VCC R1 ü 0V NOTE: Where a portion of the circuit is incorrect, the learner will lose those marks and will be awarded marks for the correct section / labels. Any 7 correct labels (7) 2.4 2.4.1 Inverting ü comparator ü (2) 2.4.2 VIN VREF 0V t +V ü ü ü 0 t ü -V 1 mark = inversion 1 mark = correct wave shape 2 marks = 1 mark for each correct trigger point. (4) 2.4.3 Change the connection of resistor R 1 ü from the positive supply to the negative supply. ü (2) 2.5 2.5.1 The gain of the amplifier is determined by the ratio ü of the feedback resistance ü to the input resistance of each branch. ü NOTE: Writing the formula only = 1 mark. (3) Copyright reserved ### Page 6 Downloaded from hlayiso.com Electrical Technology: Digital 6 DBE/November 2019 NSC – Marking Guidelines 2.5.2  R R R  VOUT = −  V1 F + V2 F + V3 F  ü  R1 R2 R3   100 × 10 3 100 × 10 3 100 × 10 3  ü  = −  0,3 × 3 + 0,5 × 3 + 0,4 ×  3   20 × 10 20 × 10 20 × 10  = −6 V ü NOTE: If the – sign is omitted in the answer, it is incorrect because it is an inverting summing amplifier. (3) 2.5.3 The amplifier is not saturated because the output voltage is less ü than the supply voltage. ü (2) 2.5.4 VOUT = VIN × Gain VOUT Gain A V = VIN ü VOUT = (V1 + V 2 + V3 ) ü −6 = (0,3 + 0,5 + 0,4 ) =−5 ü (3) 2.5.5 With a variable resistor in the feedback loop, the gain ü of the amplifier can be varied / controlled. ü (2) 2.5.6 If R 2 is changed to 10 kΩ, the gain for V 2 will increase ü causing the total output voltage to increase. ü (2) 2.6 2.6.1 RC passive ü differentiator ü NOTE: RC circuit = 1mark (2) 2.6.2 +V Input 0 t +V ü ü Output 0 t ü -V 1 mark = positive pulse 1 mark = negative pulse 1 mark = correct orientation (3) Copyright reserved ### Page 7 Downloaded from hlayiso.com Electrical Technology: Digital 7 DBE/November 2019 NSC – Marking Guidelines 2.6.3 If the circuit time constant is increased, the capacitor will discharge slower ü producing a sagging square wave. ü NOTE: If the learner draws the waveform and label correctly, mark on merit. (2) 2.7 2.7.1 C F provides a feedback connection from output to input. ü (1) 2.7.2 The inputs draw zero current. ü The two inputs possess the same voltage at all times. ü The capacitor will charge at a constant rate when a constant current is supplied. ü NOTE: If the learner gives a correct account of the operation of the integrator as applied with the 741 op-amp, the answer must be marked on merit. (3) 2.7.3 VIN 0 t ü t 0 ü ü VOUT ü -VSAT 2 marks = correct labelling 2 marks = 1 mark for each correct half cycle NOTE: The wave must be drawn correct before marks can be awarded for labelling. (4) [60] Copyright reserved ### Page 8 Downloaded from hlayiso.com Electrical Technology: Digital 8 DBE/November 2019 NSC – Marking Guidelines QUESTION 3: SEMICONDUCTOR DEVICES 3.1 3.1.1 Pin 1 is identified by being the first pin to the left and below the indentation. ü OR Being closest to the dot in the body. (1) 3.1.2 Input stage ü or differential amplifier Intermediate stage üor high gain differential amplifier Output stage ü or common collector (3) 3.1.3 • It stabilises the amplifier. ü • Distortion of the output signal is reduced. ü • The bandwidth increases. (2) 3.2 3.2.1  R  VOUT = VIN ×  − F  ü  R IN   100 × 10 3  ü = 2 ×  −  3   12 × 10  ü = −16,67 V (3) 3.2.2 The amplifier is driven into saturation ü which causes the tops and bottoms to be clipped. ü NOTE: If the learner identified that the input is fed into the inverting input, there will be a 180 degree phase shift on the output = 2 marks (2) 3.2.3 +15 volts ü –15 volts ü (2) 3.3 3.3.1 Dual in-line ü package (1) 3.3.2 Astable mode ü Monostable mode ü Bistable mode ü (3) 3.3.3 5Vü (1) 3.4 When the trigger voltage rises above the threshold voltage, the output of a 555 timer will change state ü from high to low. ü NOTE: If the answer is given as “Switch off” only = 1 mark (2) [20] Copyright reserved ### Page 9 Downloaded from hlayiso.com Electrical Technology: Digital 9 DBE/November 2019 NSC – Marking Guidelines QUESTION 4: DIGITAL AND SEQUENTIAL DEVICES 4.1 Polarisation ü (1) 4.2 4.2.1 A   B 0 Output 0  1 Output 1   2 Output 2 3 Output 3  1 mark for inputs A,B 1 mark for inverters (NOT gates) 1 mark for outputs 1 mark for AND gates 1 mark each for connections NOTE: Where a portion of the circuit is incorrect, he/she will lose those marks and will be awarded marks for the correct section / labels. (6) OR A 1 B 1 & Output 0 & Output 1 & Output 2 & Output 3 Copyright reserved ### Page 10 Downloaded from hlayiso.com Electrical Technology: Digital 10 DBE/November 2019 NSC – Marking Guidelines 4.2.2 Inputs Outputs A B 0 1 2 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 (4) TABLE 4.2.2 4.3 4.3.1 Clock  (1) 4.3.2 The driver transistors are used to feed each LED in the display separately  to ensure that all bars of a number are illuminated  to the same level.  (3) 4.3.3 Inputs Outputs A B C D a b c d e f g 0 1 0 1 1 0 1 1 0 1 1 (4) 4.4 4.4.1 A   Σ B ( sum )   Co (Carry out) 1 mark for inputs A,B 1 mark for outputs 1 mark for And gate 1 mark for XOR gate (4) OR A B =1 ∑ (sum) & Co (Carry out) Copyright reserved ### Page 11 Downloaded from hlayiso.com Electrical Technology: Digital 11 DBE/November 2019 NSC – Marking Guidelines 4.4.2 INPUTS OUTPUTS A B Σ Co 0 0 0 0  0 1 1 0 1 0 1 0  1 1 0 1 TABLE 4.4.2 (4) 4.5 4.5.1 S   Q CLK   Q  R  1 mark for input gate S 1 mark for input gate R 1 mark for output gate Q 1 mark for output gate 𝑄 1 mark for latch 1 mark for clock connection NOTE: Where a portion of the circuit is incorrect, the learner will lose those marks and will be awarded marks for the correct section / labels. (6) OR S & & Q CLK & Q & R 4.5.2 INPUTS OUTPUTS CLK S R Q � 𝐐 0 0 NO CHANGE 0 1 0  1  1 0 1 0  1 1 INDETERMINATE (4) Copyright reserved ### Page 12 Downloaded from hlayiso.com Electrical Technology: Digital 12 DBE/November 2019 NSC – Marking Guidelines 4.6 Frequency divider ü Decade counter ü Binary coded decimal (BCD) counter (2) 4.7 • When a logic low '0' is applied to the circuit it has no effect on the JK flip-flop. ü • When a logic high is applied to the inputs, the J and K inputs of each stage are held high '1' ü • Turning them each into a single stage 'toggle' that will respond to the status of its preceding stage, ü • After a clock pulse is only applied on the first flip flop it will change state. ü • Going high '1' on the first pulse and low '0' on the next pulse. ü • Rather than allow the counter to run through its full count term, a NAND gate is added with its two inputs connected to the outputs of the first and fourth flip-flop. ü • Once the count reaches 1001 (decimal 9) the NAND gate's output will trigger low '0' thus activating the 'clear' inputs of each flip-flop, ü • Re-setting them all to zero. ü and the process repeats itself. NOTE: Although the following statement is wrong, if the learner writes it in the place of the second bullet, a mark must be awarded, because it is wrongly stated in the prescribed textbook • When a logic high '1' is applied to the circuit it immediately clears or resets the flip-flop back to its original position. (8) 4.8 4.8.1 Parallel-in; Serial-out shift registerü (1) 4.8.2 A = Clock ü, B = 4-bit Parallel Data Input ü B = Input, Parallel Data Input = 1 (2) 4.8.3 In the Parallel-in Serial-out shift register all four bits of the data are introduced to the register at the same time in parallel.ü (1) 4.8.4 It is shifted out, one bit at a time ü controlled by the clock input cycle. (1) 4.8.5 The circuit enables parallel data ü to be converted ü into serial format. ü OR The circuit enables parallel data, like an 8-bit word • to be converted into serial format, or • to mix a number of input lines together into a single stream of data • that can be sent directly to a computer or be transmitted over a communication line. (3) [55] Copyright reserved ### Page 13 Downloaded from hlayiso.com Electrical Technology: Digital 13 DBE/November 2019 NSC – Marking Guidelines QUESTION 5: MICROCONTROLLERS 5.1 A microcontroller is a computer presented in a single integrated circuit ü which is dedicated to perform a task/s ü and execute one specific application. ü OR A microcontroller is an independent device, a computer on a chip that can perform a limited range of functions without needing to rely on other chips or devices. (3) 5.2 5.2.1 First, it fetches instructions and data from memory. ü It then decodesü the instructions which are written in binary code, then it executes üthe instruction before starting the cycle all over again. OR The operating cycle of a CPU follows a 'fetch-decode-execute’ cycle. The operating cycle of a CPU follows a ‘Input-Process-Output’ cycle. (3) 5.2.2 The CIR holds the instruction ü that is currently being executed ü at a specific address. ü OR • The Current Instruction Register (CIR) splits the instruction into two parts. • One part is decoded by the control unit ready for execution. • The other part is the address of the data stored that needs to be used together with that instruction. (3) 5.2.3 The ADC detects a continuously variable (analogue) signal and changes ü this analogue signal, ü without altering its essential content, into a multi-level (digital) signal. ü (3) 5.2.4 • The timer is programmed to count to a predetermined number. ü • Data is fed into the CIR via the MDB in parallel. ü • The clock pulses together with the number being counted to determine the time duration. ü • When the 8-bit count finally overflows the register, an output signal is generated on the following clock pulse. ü • This could trigger an interrupt in the processor or set a bit that the processor can read. ü • Once done the register is cleared on the next clock pulse. ü OR The timer accepts data, one bit at a time, controlled by the pulse rate of the clock, incrementing (adding one by one) for each pulse until the register overflows. (6) Copyright reserved ### Page 14 Downloaded from hlayiso.com Electrical Technology: Digital 14 DBE/November 2019 NSC – Marking Guidelines 5.3 • The RAM stores all the data that is required to be processed by the CPU during the execution of programmes. ü OR • RAM can both read and write data into it. • It can hold programmes, operating systems and data required by the system. (1) 5.4 5.4.1 • Simplex ü • Duplex ü • Half-duplex • Full-duplex (2) 5.4.2 • Faster ü • Higher Bandwidth ü (More bits can be transferred in a shorter time) (2) 5.4.3 • The system needs a clock signal to both transmitter and receiver. ü • It operates on a primary/secondary configuration where one system (the transmitter) has control over the operation and the receiver is the secondary. ü • The systems need to be synchronised. (2) 5.5 • Inter-integrated bus (I2C) is a powerful two wire bus ü • That can support up to one thousand slave devices ü • as well as supporting the communication of multiple masters ü • Which, cannot talk to each other over the bus and have to take turns in using the bus lines. • I2C uses start and stop sequences between masters and slaves over a two wire system. • It works on a master-slave principle. (3) 5.6 5.6.1 Master ü (1) 5.6.2 Serial Clock Line ü (1) 5.6.3 Pull-up resistors, connected to a +5 V supply, are necessary for the lines (SCL and SDA) ü to go high. ü (2) 5.6.4 A slave cannot initiate a transfer over the I2C bus. ü A slave interprets instructions received by the master. (1) 5.6.5 • I2C requires only two wires ü • I2C supports multiple devices on the same bus without additional select lines ü • I2C ensures that data sent is received by the slave device. ü • I2C is cheaper to implement • I2C supports multiple master devices • I2C is less susceptible to noise than SPI (3) 5.7 5.7.1 Logic '1' between -3 V and -25 V ü Logic '0' between +3 V and +25 V ü (2) Copyright reserved ### Page 15 Downloaded from hlayiso.com Electrical Technology: Digital 15 DBE/November 2019 NSC – Marking Guidelines 5.7.2 Used in low-data-rate short range applications such as; • printers, ü • modems, ü • data projectors, ü • CNC machine tools (3) 5.8 5.8.1 A program is a sequence of instructions ü that informs a computer how to perform a task. ü (2) 5.8.2 A flow diagram is a visual representation of steps and decisions ü needed to perform and complete a process. ü (2) Copyright reserved ### Page 16 Downloaded from hlayiso.com Electrical Technology: Digital 16 DBE/November 2019 NSC – Marking Guidelines 5.9  Start  Sensor? No Yes   Siren on   Reset? No Yes   Siren off 1 mark for Start symbol (1) 1 mark for Sensor symbol (1) 1 mark for Siren on symbol (1) 1 mark for Reset symbol (1) 1 mark for Siren off symbol (1) 1 mark for any one YES/NO statement (2) 1 mark each for THREE correct flow lines (3) (10) NOTE: Each design must be assessed on merit and variations should be allowed. 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