# Electrical Technology Grade 12 NSC November 2019 Memo (Eng) > Grade 12 Electrical Technology memorandum from the NSC November Exam 2019 (English), 17 pages. Read online or download the free PDF. - Page: https://www.hlayiso.com/library/electrical-technology-nov-2019-electronics-memo-eng/dfabd9d1-4672-443e-9018-3561479cab48 - Updated: 2026-09-27 - Subject: Electrical Technology - Grade: Grade 12 - Document type: Memorandum - Year: 2019 - Exam period: NSC November Exam - Curriculum: CAPS - Pages: 17 Breadcrumbs: [Home](https://www.hlayiso.com/) › [Library](https://www.hlayiso.com/library) › [Grade 12](https://www.hlayiso.com/library/grade-12) › [Electrical Technology](https://www.hlayiso.com/library/grade-12/electrical-technology) › [Electrical Technology Grade 12 NSC November 2019 Memo (Eng)](https://www.hlayiso.com/library/electrical-technology-nov-2019-electronics-memo-eng/dfabd9d1-4672-443e-9018-3561479cab48) ## About this document Electrical Technology · Grade 12 · NSC November Exam · 2019. Memorandum, 17 pages. Read online or download the PDF. Read it free online on the page above; download the PDF from there. ## Document text Text extracted from the PDF. Layout, diagrams and tables may not survive extraction. ### Page 1 Downloaded from hlayiso.com NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: ELECTRONICS NOVEMBER 2019 MARKING GUIDELINES MARKS: 200 These marking guidelines consist of 17 pages. Copyright reserved Please turn over ### Page 2 Downloaded from hlayiso.com Electrical Technology: Electronics 2 DBE/November 2019 NSC – Marking Guidelines INSTRUCTIONS TO THE MARKERS 1. All questions with multiple answers imply that any relevant, acceptable answer should be considered. 2. Calculations: 2.1 All calculations must show the formulae. 2.2 Substitution of values must be done correctly. 2.3 All answers MUST contain the correct unit to be considered. 2.4 Alternative methods must be considered, provided that the correct answer is obtained. 2.5 Where an incorrect answer could be carried over to the next step, the first answer will be deemed incorrect. However, should the incorrect answer be carried over correctly, the marker has to re- calculate the values, using the incorrect answer from the first calculation. If correctly used, the candidate should receive the full marks for subsequent calculations. 2.6 Markers should consider when and where a candidate has rounded off in a calculation, as well as the subsequent effect it has on the final answer obtained. The calculation should therefore be awarded marks on merit. 3. This marking guideline is only a guide with model answers. Alternative interpretations must be considered and marked on merit. However, this principle should be applied consistently throughout the marking session at ALL marking centres. Copyright reserved Please turn over ### Page 3 Downloaded from hlayiso.com Electrical Technology: Electronics 3 DBE/November 2019 NSC – Marking Guidelines QUESTION 1: OCCUPATIONAL HEALTH AND SAFETY 1.1 • Teamwork helps a team to meet its goals. ü • Teamwork helps a team deliver quality work ü • Teamwork can win the respect of your co-workers. • Working together as a team can improve discipline in the workshop. • Teamwork will lead to improved productivity. (2) 1.2 1.2.1 The purpose of the Act is to: • Provide for health and safety of persons at work. ü • Protect against hazards arising from the activities of other people at work. ü • Establish an advisory council for occupational health and safety and related matters. • Provide for health and safety for persons in connection with the use of plant and machinery (2) 1.2.2 Workplace can be defined as any premises or place where a person performs work ü during the time of his employment. ü (2) 1.3 1.3.1 Employee. ü Learner, Supervisor, Team leader, Safety representative (1) 1.3.2 Health and safety representative. ü Inspector. (1) 1.4 • Remain calm ü • Stop whatever you are doing and switch off machinery. ü • Notify a responsible adult or teacher. • If there is an emergency stop nearby activate it if necessary. • Move in an orderly manner to the nearest assembly point. NOTE: Procedure can be listed in any order. (2) [10] Copyright reserved Please turn the page ### Page 4 Downloaded from hlayiso.com Electrical Technology: Electronics 4 DBE/November 2019 NSC – Marking Guidelines QUESTION 2: RLC CIRCUITS 2.1 2.1.1 Power factor is the ratio ü of the true power to the apparent power. ü NOTE: If the formula is written 1 mark must be awarded (2) 2.1.2 The quality factor of an inductor refers to the ratio of the inductor's reactance ü to its internal resistance during resonance. ü If the formula is written 1 mark must be awarded The ratio of the inductive/capacitive voltage to the supply voltage during resonance The ratio of the inductive/capacitive reactance to the impedance during resonance (2) 2.2 • Wattless voltage dividers ü • Timing circuits ü • Filter circuits • Oscillating circuits • Radio-tuning circuits (2) 2.3 2.3.1 VT = VR + (VC − VL ) 2 2 ü = 12 2 + (24 − 16 ) ü 2 = 14,42 V ü (3) 2.3.2 VL XL = ü I 16 = ü 3 = 5,33 Ω ü (3) 2.3.3 The circuit is capacitive ü because the voltage drop across the capacitor is greater than the voltage across the inductor. ü NOTE: If X L and X C are calculated and stated as a capacitive circuit, 2 marks should be awarded. If the learner wrote, the circuit is inductive, but give the same reason, that motivation is deemed incorrect. (2) Copyright reserved Please turn the page ### Page 5 Downloaded from hlayiso.com Electrical Technology: Electronics 5 DBE/November 2019 NSC – Marking Guidelines 2.3.4 VL = 16 V ü VR = 12 V θü IT = 3 A ü (VC-VL) ü =8V VT = 14,42 V VC = 24 V NOTE: No label, no marks (4) 2.3.5 When the impedance of the circuit is increased, the power factor will decrease ü therefore increasing the value of the phase angle. ü (2) 2.4 2.4.1 2 ü IT = IR + (IL − IC ) 2 ü = 6 2 + (4 − 3 ) 2 ü = 6,08 A (3) 2.4.2 I ü Cos θ = R IT I ü θ = Cos −1 R IT 6 = Cos −1 6,08 ü = 9,30  (3) 2.4.3 The phase angle is lagging ü because the inductive current is larger than the capacitive current. ü NOTE: If only the second part of the answer is given = 1 mark (2) Copyright reserved Please turn the page ### Page 6 Downloaded from hlayiso.com Electrical Technology: Electronics 6 DBE/November 2019 NSC – Marking Guidelines 2.5 2.5.1 At resonance X L = X C = 50 Ω ü 1 C= ü 2 π f XC 1 ü = 2 × π × 2000 × 50 = 1,59 μF ü (4) NOTE: If the learner only substituted 50 Ω in the place of X C , the correct substitution will be awarded 2 marks If the learner calculated the inductance first, and used the resonant frequency’s formula to work out the capacitance full marks must be awarded. XL L= 2 × πf 50 L= 2 × π × (2000) L = 3,98 × 10−3 H 1 fr = 2π LC 1 2000 = 2π 3,97 × 10 − 3 × C ( ) 2000 2π 3,97 × 10 − 3 × C = 1 C = 1,6 μF 2.5.2 At resonance R = Z = 12 Ω ü V I= T ü Z 120 = ü 12 = 10 A ü (4) If R is used in the place of Z, full marks are awarded 2.5.3 If the resistance is doubled, the current will be halved. ü (1) 2.5.4 Z=R ü VL = VC ü ü VR = VT XL = X C Cos θ = 1 θ = 0° I = maximum Z = minimum (3) [40] Copyright reserved Please turn the page ### Page 7 Downloaded from hlayiso.com Electrical Technology: Electronics 7 DBE/November 2019 NSC – Marking Guidelines QUESTION 3: SEMICONDUCTOR DEVICES 3.1 N-type ü semiconductor material. (1) 3.2 N-channel JFET. ü DRAIN (D) ü GATE (G) ü SOURCE (S) NOTE: The symbol must be drawn correctly to receive marks for labelling. (3) 3.3 3.3.1 P-channel. ü (1) 3.3.2 The drain must be connected to positive. ü The source must be connected to negative. ü The gate voltage must be positive. ü (3) 3.4 3.4.1 Switch ü Oscillators Phase Control circuits Timing circuits (1) 3.4.2 The UJT triggers when the voltage across the capacitor / emitter rises ü to 0,7 V above the intrinsic standoff ratio (V X or V BB ). ü The UJT triggers on when the voltage across the capacitor / emitter rises to the UJT's peak voltage V P . (2) Copyright reserved Please turn the page ### Page 8 Downloaded from hlayiso.com Electrical Technology: Electronics 8 DBE/November 2019 NSC – Marking Guidelines 3.4.3 VC Input ü Output ü ü (3) 3.5 3.5.1 Pin 1 is identified by being the first pin to the left and below the indentation. ü OR Being closest to the dot in the body of the IC. (1) 3.5.2 Input stageü or differential amplifier Intermediate stage üor high gain differential amplifier Output stage ü or common collector (3) 3.6 3.6.1  R  VOUT = VIN ×  − F  ü  R IN   100 × 10 3  ü = 2 ×  −  3   12 × 10  ü = −16,67 V (3) 3.6.2 The amplifier is driven into saturation ü which causes the tops and bottoms to be clipped. ü If the learner identified that the input is fed into the inverting input, there will be a 180 degree phase shift on the output = 2 marks (2) 3.6.3 +15 voltsü –15 voltsü (2) 3.7 3.7.1 Dual in-line ü package (1) 3.7.2 16 V ü (1) 3.7.3 5Vü (1) 3.8 When the trigger voltage rises above the threshold voltage, the output of a 555 timer will change state ü from high to low. ü NOTE: If the answer is given as “Switch off” only = 1 mark (2) [30] Copyright reserved Please turn the page ### Page 9 Downloaded from hlayiso.com Electrical Technology: Electronics 9 DBE/November 2019 NSC – Marking Guidelines QUESTION 4: SWITCHING CIRCUITS 4.1 4.1.1 A – Bistable multivibrator ü B – Monostable multivibrator ü (2) 4.1.2 ü +V 0 t ü -V 2 marks = 1 mark for each correct half cycle If waveform is drawn correctly, but inverted, 2 marks will be awarded NOTE: Due to the +V instead of -V typo on the answer sheet, the following responses are also accepted. (2) +V +V +V ü ü ü ü ü ü 0 0 0 4.2 4.2.1 Resistors R 1 and R 2 are pull-up resistors. üü R 1 and R 2 hold both trigger pin 2 and reset pin 4 high. (2) 4.2.2 When set switch S 1 is pressed, trigger pin 2 will be pulled low ü and cause the IC output to 'flip' and rise high ü turning the LED on. ü (3) 4.2.3 Threshold pin 6 is purposefully held at 0 V ü causing the IC not to reset, ü keeping the output high ü when S 1 is pressed, (3) 4.3 4.3.1 The output signal represents an inverting Schmitt trigger ü because the output signal is inverted ü with reference to the input signal. ü OR The output signal is at -V CC when triggered by the upper trigger voltage and swings to +V CC when triggered by the lower trigger voltage. (3) Copyright reserved Please turn the page ### Page 10 Downloaded from hlayiso.com Electrical Technology: Electronics 10 DBE/November 2019 NSC – Marking Guidelines 4.3.2 ü ü + VCC VIN ü ü VOUT ü RF ü -VCC R1 ü 0V NOTE: Where a portion of the circuit is incorrect, he/she will lose those marks and will be awarded marks for the correct section / labels. Any 7 correct labels (7) 4.4 4.4.1 Inverting ü comparator ü (2) 4.4.2 VIN VREF 0V t +V ü ü ü 0 t ü -V 1 mark = inversion 1 mark = correct wave shape 2 marks = 1 mark for each correct trigger point. (4) 4.4.3 Change the connection of resistor R 1 ü from the positive supply to the negative supply. ü (2) 4.5 4.5.1 The gain of the amplifier is determined by the ratio ü of the feedback resistance ü to the input resistance of each branch. ü NOTE: Writing the formula only = 1 mark. (3) Copyright reserved Please turn the page ### Page 11 Downloaded from hlayiso.com Electrical Technology: Electronics 11 DBE/November 2019 NSC – Marking Guidelines 4.5.2  R R R  VOUT = −  V1 F + V2 F + V3 F  ü  R1 R2 R3   100 × 10 3 100 × 10 3 100 × 10 3  ü = −  0,3 × + 0,5 × + 0,4 ×   20 × 10 3 20 × 10 3 20 × 10 3  ü = −6 V NOTE: If the – sign is omitted in the answer, it is incorrect because it is an inverted summing amplifier. (3) 4.5.3 The amplifier is not saturated because the output voltage is less ü than the supply voltage. ü (2) 4.5.4 VOUT = VIN × Gain VOUT Gain A V = ü VIN VOUT = (V1 + V 2 + V3 ) −6 = ü (0,3 + 0,5 + 0,4 ) =−5 ü (3) 4.5.5 With a variable resistor in the feedback loop, the gain ü of the amplifier can be varied / controlled. ü (2) 4.5.6 If R 2 is changed to 10 kΩ, the gain for V 2 will increase ü causing the total output voltage to increase. ü (2) 4.6 4.6.1 RC ü passive differentiator ü NOTE: RC circuit = 1mark (2) 4.6.2 +V Input 0 t +V ü ü Output 0 t ü -V 1 mark = positive pulse 1 mark = negative pulse 1 mark = correct orientation (3) 4.6.3 If the circuit time constant is increased, the capacitor will discharge slower ü producing a sagging square wave. ü NOTE: If the learner draws the waveform and label correctly, mark on merit. (2) Copyright reserved Please turn the page ### Page 12 Downloaded from hlayiso.com Electrical Technology: Electronics 12 DBE/November 2019 NSC – Marking Guidelines 4.7 4.7.1 C F provides a feedback connection from output to input. ü (1) 4.7.2 The inputs draw zero current. ü The two inputs will have the same voltage at all times. ü The capacitor will charge at a constant rate when a constant current is supplied. ü NOTE: If the learner gives a correct account of the operation of the integrator as applied with the 741 op-amp, the answer must be marked on merit. (3) 4.7.3 VIN 0 t ü t 0 ü ü VOUT ü -VSAT 2 marks = correct labelling 2 marks = 1 mark for each correct half cycle NOTE: The wave must be drawn correct before marks can be awarded for labelling. (4) [60] Copyright reserved Please turn the page ### Page 13 Downloaded from hlayiso.com Electrical Technology: Electronics 13 DBE/November 2019 NSC – Marking Guidelines QUESTION 5: AMPLIFIERS 5.1 5.1.1 Q Point Class A Amplifier - The Q point is in the middle of the DC load line.ü Class B Amplifier - The Q point is on the cut-off of the DC load line.ü NOTE: If a learner draws the Q point instead of a narrative answer, mark on merit (2) 5.1.2 Efficiency Class A Amplifier - It has low efficiency therefore it has less output power.ü Class B Amplifier - It has higher efficiency therefore produces more output power.ü Class A Amplifier - 25% Class B Amplifier - 50% (2) 5.2 5.2.1 To limit the current flowing through the collector. ü Protects the circuit from damage. To protect the transistor. (1) 5.2.2 When the transistor is OFF, no collector current flows through it,ü therefore the maximum supply voltage will appear across the transistor.ü OR From the formula VCC = VCE + ICRC If I C = 0 then (I C R C = 0) therefore (V CC = V CE ) (2) 5.3 In Class C amplification, a transistor is biased below the cut off region ü therefore the collector current flows for less than 180°. ü (2) 5.4 5.4.1 Class A amplifier. +V Phase ü relationship ü 0 t ü -V 1 mark = phase relationship 2 marks = 1 mark for each correct half cycle (3) Copyright reserved Please turn the page ### Page 14 Downloaded from hlayiso.com Electrical Technology: Electronics 14 DBE/November 2019 NSC – Marking Guidelines 5.4.2 Class AB amplifier +V ü Phase ü relationship 0 t ü -V 1 mark = phase relationship 2 marks = 1 mark for each correct half cycle (3) 5.5 • It can lead to the increases in currents leading to thermal runaway, which could destroy the transistor. ü • Crossover point distortion may occur. • Incorrect placement of the Q-point • Non-linear amplification (Distortion) • Changes in the power supply voltage can cause the transistor's currents to change. NOTE: Bullet 5 is not an undesirable condition, but will be accepted because it is stated in the prescribed textbook. (1) 5.6 5.6.1 The emitter is common ü to both the input and the output circuits.ü (2) 5.6.2 Input signal will be connected between point B and C. ü The load can be connected between point E and F. ü (2) 5.6.3 Emitter capacitor (C E ) ü Emitter resistor (R E ) ü (2) 5.6.4 ü Inversion DC offset ü OR Q-point ü 0 t 1 mark = inversion 2 marks = 1 mark for each amplified half cycle (3) Copyright reserved Please turn the page ### Page 15 Downloaded from hlayiso.com Electrical Technology: Electronics 15 DBE/November 2019 NSC – Marking Guidelines 5.6.5 ü Inversion +V ü 0 t ü -V 1 mark = inversion 2 marks = 1 mark for each amplified half cycle (3) 5.7 • Impedance matching.ü • Correct frequency response.ü • DC isolation. (2) 5.8 5.8.1 POUT ü A P = 10 log10 PIN ü 1200 = 10 log10 3015 = − 4 dB ü (3) 5.8.2 VOUT ü A V = 20 log10 VIN 219 ü = 20 log10 230 = − 0,43 dB ü (3) 5.9 The gain of an amplifier is the capability of an amplifier to increase the magnitude of the input signal ü without distortion.ü Gain is the ratio of how much bigger or smaller the output signal will be bigger in comparison to the input signal. (2) 5.10 A V = A V1 × A V2 × A V3 ü = 10 × 15 × 20 ü = 3000 ü (3) 5.11 5.11.1 Complimentary - symmetry ü Push-pull Amplifier. ü (2) 5.11.2 Cross-over distortion is eliminated by biasing the two push pullü transistors each into class AB mode. ü Cross-over distortion is eliminated by biasing the two push pull transistors just above the cut-off region. (2) 5.11.3 The resistors are used for correct biasing ü (1) Copyright reserved Please turn the page ### Page 16 Downloaded from hlayiso.com Electrical Technology: Electronics 16 DBE/November 2019 NSC – Marking Guidelines 5.11.4 +V ü ü Phase relationship 0 ü t -V 1 mark = phase relationship 2 marks = 1 mark for each amplified half cycle NOTE: If the learner indicated cross-over distortion on the waveform, it will be accepted because of the two transistors used in the given circuit If the frequency is wrong, the waveform is wrong. (3) 5.12 5.12.1 RC oscillator - Does not use a resonating tank circuit but uses selective resistors and capacitors in the feedback network. ü LC oscillator - Uses tank circuit in the feedback network between the Drain and the Gate of the transistor. ü (2) 5.12.2 LC oscillators - The oscillating frequency is determined by the values of the capacitors and inductor in the tank circuit. ü (Colpitts oscillator) OR The oscillating frequency is determined by the values of the inductors and a capacitor in the tank circuit.(Hartley oscillator) RC oscillator - the oscillating frequency is determined by the values of the resistors and the capacitors in the feedback circuit. ü (2) Copyright reserved Please turn the page ### Page 17 Downloaded from hlayiso.com Electrical Technology: Electronics 17 DBE/November 2019 NSC – Marking Guidelines 5.13 C ü ü ü L1 L2 (3) 5.14 Provide a phase shift of 180 degrees. ü Amplifies the signal from the tank circuit. ü (2) 5.15 Both their output waveforms are purely sinusoidal. ü They both use a transistor for amplification. ü They both use resistors for biasing. They both use positive feedback to operate. Both circuit’s feedback circuits creates a 180° phase shift. Both circuit’s transistor configuration creates 180° phase shift. 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