# Electrical Technology Grade 12 NSC November 2022 Memo (Eng) > Grade 12 Electrical Technology memorandum from the NSC November Exam 2022 (English), 16 pages. Read online or download the free PDF. - Page: https://www.hlayiso.com/library/electrical-technology-nov-2022-digital-mg-eng/bf2888f5-bd73-4eab-9216-1c1d5595f252 - Updated: 2026-10-29 - Subject: Electrical Technology - Grade: Grade 12 - Document type: Memorandum - Year: 2022 - Exam period: NSC November Exam - Curriculum: CAPS - Pages: 16 Breadcrumbs: [Home](https://www.hlayiso.com/) › [Library](https://www.hlayiso.com/library) › [Grade 12](https://www.hlayiso.com/library/grade-12) › [Electrical Technology](https://www.hlayiso.com/library/grade-12/electrical-technology) › [Electrical Technology Grade 12 NSC November 2022 Memo (Eng)](https://www.hlayiso.com/library/electrical-technology-nov-2022-digital-mg-eng/bf2888f5-bd73-4eab-9216-1c1d5595f252) ## About this document Electrical Technology · Grade 12 · NSC November Exam · 2022. Memorandum. Read online or download the PDF. Read it free online on the page above; download the PDF from there. ## Document text Text extracted from the PDF. Layout, diagrams and tables may not survive extraction. ### Page 1 Downloaded from hlayiso.com NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: DIGITAL ELECTRONICS NOVEMBER 2022 MARKING GUIDELINES MARKS: 200 These marking guidelines consist of 16 pages. Copyright reserved Please turn over ### Page 2 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 2 DBE/November 2022 NSC – Marking Guidelines INSTRUCTIONS TO THE MARKERS 1. All questions with multiple answers imply that any relevant, acceptable answer should be considered. 2. Calculations: 2.1 All calculations must show the formulae. 2.2 Substitution of values must be done correctly. 2.3 All answers MUST contain the correct unit to be considered. 2.4 Alternative methods must be considered, provided that the correct answer is obtained. 2.5 Where an incorrect answer could be carried over to the next step, the first answer will be deemed incorrect. However, should the incorrect answer be carried over correctly, the marker has to re- calculate the values, using the incorrect answer from the first calculation. If correctly used, the candidate should receive the full marks for subsequent calculations. 3. These marking guidelines are only a guide with model answers. Alternative interpretations must be considered and marked on merit. However, this principle should be applied consistently throughout the marking session at ALL marking centres. Copyright reserved Please turn over ### Page 3 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 3 DBE/November 2022 NSC – Marking Guidelines QUESTION 1: MULTIPLE-CHOICE QUESTIONS 1.1 C (1) 1.2 A (1) 1.3 C (1) 1.4 D (1) 1.5 C (1) 1.6 D  (1) 1.7 C (1) 1.8 D (1) 1.9 D (1) 1.10 A (1) 1.11 B (1) 1.12 D (1) 1.13 A (1) 1.14 C (1) 1.15 B (1) [15] Copyright reserved Please turn over ### Page 4 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 4 DBE/November 2022 NSC – Marking Guidelines QUESTION 2: OCCUPATIONAL HEALTH AND SAFETY 2.1 The employer should be respected  The employer should not be discriminated against.  Your right to fair labour practices. Your right to work reasonable hours. Your right to belong to a trade union. Your right to earn a living wage. Your right not to be discriminated against. (2) 2.2 Move in an orderly manner.  Follow the evacuation route as displayed in your workshop.  Move to the designated assembly point in a calm and orderly manner. (2) 2.3 Misusing equipment is a dangerous practice which might damage the equipment  and render it unsafe, compromising the safety and or threatens the health of others.  (2) 2.4 An employer shall not dismiss an employee  without the correct procedures being followed. An employer shall not reduce the remuneration of an employee as punishment. Alter terms of condition of employment to one that is less favourable.  Alter a position relative to other employees employed by that employer to disadvantage them. (2) 2.5 Quantitative risk analysis Qualitative risk analysis (2) [10] Copyright reserved Please turn over ### Page 5 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 5 DBE/November 2022 NSC – Marking Guidelines QUESTION 3: SWITCHING CIRCUITS 3.1 The output of a monostable multivibrator has only one stable state.  The output of an astable multivibrator will toggle between high and low states continuously.  The output of an astable multivibrator has no stable state. (2) 3.2 3.2.1 The bistable multivibrator is used in automated applications.  (where a device is required to run continuously back and forth on the same path) Counting circuits. Storing circuits. Frequency divider circuits. Latches. (1) 3.2.2 To prevent the IC from resetting.  When a positive pulse (trigger pulse 1) is applied to the Trigger input, the output will change to low (0 V)  and remain there until a low pulse (trigger pulse 2) is applied.  (3) 3.2.3 Without pull-up resistor R2 connected to the supply, the voltage on pin 2 will continuously vary  between VCC and 0 V.(floating) (2) 3.2.4 VCC Trigger input when S1 is pressed 0V VCC Trigger input when S2 is pressed 0V VCC  Output 0V   NOTE: An inverted output waveform the candidate will lose 1 mark for orientation and be awarded 2 marks for the correct trigger points. (3) 3.3 3.3.1 C2 and R3 sets the time period  that the circuit will remain in its changed state.  (2) 3.3.2 0V (1) 3.3.3 The moment a positive pulse is applied to the inverting input, the output changes from positive saturation (9 V)  to negative saturation (-9 V)  for the duration of the RC time constant.  (3) Copyright reserved Please turn over ### Page 6 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 6 DBE/November 2022 NSC – Marking Guidelines 3.3.4 VIN   +9 V  VOUT Orientation  -9 V VB NOTE: An exact inverted output waveform will lose 1 mark for orientation and be awarded 3 marks. (4) 3.4 3.4.1 Positive  (1) 3.4.2 The output changes from +9 V to –9 V the moment VA (inverting voltage) becomes higher than VB. (non-inverting voltage)  (1) 3.4.3 An increase in the value of RF will increase the RC time constant  on the input of the op amp, because the capacitor takes longer to charge up to the voltage VB,  it results in a decrease in frequency on the output.  (3) 3.5 3.5.1 +9 V and -9 V  (1) 3.5.2 RF and R1 used to determine the trigger voltage level  on the non- inverting input.  If a candidates mention that RF and R1 is a voltage divider 1 mark is allocated. (2) 3.5.3 The output changes from high to low when the input voltage (Vin) is higher  than the upper trigger voltage (VX).  (2) Copyright reserved Please turn over ### Page 7 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 7 DBE/November 2022 NSC – Marking Guidelines 3.6  The op amp compares the voltages appearing on its two input terminals.   When the input voltage on the inverting input is lower than the reference voltage   the op amp is driven to positive saturation.   As soon as the input on the inverting terminal is higher than the reference voltage,  the op amp is driven into negative saturation. (3) 3.7 3.7.1 Inverting summing amplifier.  (1) 3.7.2 The gain of the amplifier is -1,  because R1=R2=R3=RF  (2) 3.7.3    (3) ( ) ( ) 3.7.4 An increase in the value of the feedback resistor will decrease negative feedback  resulting in an increase in the gain.  Gain will increase, therefore output voltage will also increase. (2) 3.8 3.8.1 How long the input voltage has been present.  The value of the input voltage.  The frequency Value of the resistor and capacitor The RC-time constant The value of the supply voltage (2) 3.8.2 Both inputs to the op amp are kept at 0 V  according to Ohm's law when a constant positive voltage is applied across the input resistor it causes a constant fixed current to flow,  which is fed via the virtual ground point to the capacitor,  this means that the voltage on its right- hand plate will decrease at a fixed linear rate towards -V.  (4) 3.8.3 When the RC time constant is long, the capacitor will charge slowly causing the slope of the output to decrease.  The output will change direction before reaching saturation. (2) [50] Copyright reserved Please turn over ### Page 8 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 8 DBE/November 2022 NSC – Marking Guidelines QUESTION 4: SEMICONDUCTOR DEVICES 4.1 4.1.1 0V If a learner refers to ‘virtual ground’ it will be accepted. (1) 4.1.2 RF AV    RIN 1400   1000   1,4  (3) 4.1.3 The output signal will have a 180º phase shift.  The output signal will be inverted. (1) 4.2 4.2.1 Along DA and BE of the graph FIGURE B (2) 4.2.2 VOUT AC  AV   VIN OC   13  1   13  (3) 5.1.1. 5.1.2. 5.1.3. 4.2.3 +V 1 Input t -1 -V +VSAT   Orientation Output t  -VSAT (3) 4.2.4 The gain of the amplifier will increase.  Output voltage will be increased.  (2) 4.3 4.3.1 Pin 7 provides the discharge path for the timing capacitor and timing resistor.  Pin 7 provides a discharge path to ground. (1) 4.3.2 When the voltage at Pin 2 falls below 1/3  of the supply voltage,  it pulls Pin 2 to ground , the output goes high,  thereby activating the 555 circuit. (4) [20] Copyright reserved Please turn over ### Page 9 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 9 DBE/November 2022 NSC – Marking Guidelines QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.1 5.1.1 A = any acceptable value between the range of 3 V to 18 V  Supply voltage will be accepted B = Clock Input  (2) 5.1.2 The main purpose of the driver is to provide the necessary current  to activate the seven-segment display.  A seven-segment display driver is used to convert a four-bit binary code to a seven-segment binary code to that the seven-segment display can show a decimal number for the user. (2) 5.2 P A B P P 0 Output 0 P 1 Output 1 2 Output 2 P 3 Output 3 (5) 5.3 5.3.1 X = XOR  Y = AND  (2) Copyright reserved Please turn over ### Page 10 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 10 DBE/November 2022 NSC – Marking Guidelines 5.3.2 A B Σ cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 (6) 5.4 1 2 3 4 5 6 CLK J K       Q OR 1 2 3 4 5 6 CLK J K       Q (6) Copyright reserved Please turn over ### Page 11 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 11 DBE/November 2022 NSC – Marking Guidelines 5.5 5.5.1 Active Low Latch ( ̅ ̅ latch) (1) 5.5.2 INPUTS OUTPUTS INPUTS OUTPUTS S R Q Q S R Q Q 0 0 Unpredictable 0 0 1 1  0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 1 No change 1 1 No change NOTE: The first table is correct, but the second table will also be accepted as it is from the textbook. (6) 5.6 5.6.1 Up-counter is simply a digital counter that counts up  to some predefined increment.  (2) 5.6.2 Up/down is a counter that can change state in either direction, under the control of an up/down selector input.  (2) 5.6.3 A ripple counter is a type of asynchronous counter in which the clock pulse ripples through the circuit.  OR Ripple counter consists of a series connection of complementing flip- flops and the output of each flip-flop is connected to the clock input of the next higher-order flip-flop. (2) 5.7 5.7.1 7 8 1 2 3 4 5 6 CLK A     B     C (8) 5.7.2 The Down counter has fewer logic gates  than the Up/Down counter thereby reducing propagation delay  causing it to operate faster. (2) Copyright reserved Please turn over ### Page 12 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 12 DBE/November 2022 NSC – Marking Guidelines 5.8     High mux D Q mux D Q mux D Q mux D Q  output     CLK Q CLK Q CLK Q CLK Q Clock PD PC PB PA (9) [55] Copyright reserved Please turn over ### Page 13 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 13 DBE/November 2022 NSC – Marking Guidelines QUESTION 6: MICROCONTROLLERS 6.1 CPU   RAM   INPUT/ OUTPUT  ROM NOTE: 1 mark for each correctly labelled block (x 4) 1 mark for all connecting lines (1) If the learners showed all the components but incorrectly placed (2) (5) 6.2 It fetches each instruction  that needs to be executed in a program  by issuing control signals to the hardware.  It then decodes the instruction  and finally issues more control signals to the hardware to actually execute it.  (5) 6.3 6.3.1 The TRIS register sets the 'direction' of the input  and output pins  by setting some bits of the TRIS register to either '0' or '1'. (2) 6.3.2 By setting the TRIS register bits low '0' configures the pins as 'output' pins  and setting the register bits to high '1' configures the same pins to 'input' pins.  (2) 6.4 The majority of input signals from inputs are of an analogue nature  whereas the microcontroller operates purely in digital.  Therefore A/D converters are needed to convert the analogue input signals to digital.  (3) 6.5 6.5.1 A = Transmitter/Sender  B = Receiver  C = Request  (3) Copyright reserved Please turn over ### Page 14 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 14 DBE/November 2022 NSC – Marking Guidelines 6.5.2  Data is sent in a pre-arranged pattern of bits called bytes.   There is no timing signal or clock pulse required.   The flow of data from the sender to the receiver is monitored/ checked by the parity bits, namely the 'start bit', usually binary '0', and the 'stop bit' which are added at the beginning and at the end of each byte.   Data moves one byte at a time   When a sender receives data, it sends a request to the receiver and waits for an acknowledge signal   Once the signal is received, the sender then sends the data together with the start and stop parity bits  (6) OR  Data is sent in a pre-arranged pattern of bits.  Once both ends of the system (sender and receiver) have agreed on the pattern then communication can take place, with no timing signal or clock pulse required.  'Parity' bits are added to the front and end of each binary byte or small group of bits.  A parity bit is simply an additional bit added to a block of binary bits to keep a check on their order.  Bits are grouped together consisting of both data and control bits. If the signal is not synchronised the receiver will not be able to distinguish when the next group of bits will arrive.  To overcome this the data is preceded by a 'start bit', usually binary '0', the byte is then sent and a 'stop bit' which is added to the end.  Each byte to be sent now incorporates extra control data. In addition to the control data, small gaps are inserted between each 'chunk' to distinguish each group. 6.5.3 It does not need a synchronising clock pulse between sender and receiver.  It is a 'peer-to-peer' system where data can be transferred in both directions between the two devices.  (2) 6.6 6.6.1 Serial Peripheral Interface.  (1) 6.6.2 Full duplex mode.  (1) 6.6.3  The SPI communicates in full duplex mode.  Communication is initiated by the master, generating the clock signal through SCK to the port pin of the slave  The master switches the SS pin to a low voltage state which activates the slave   The master sends the data one bit at a time to the slave along the MOSI line. The slave reads the bits as they are received   If a response is needed, the slave returns data one bit at a time to the master along the MISO line   The master reads the bits as they are received  (4) OR Copyright reserved Please turn over ### Page 15 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 15 DBE/November 2022 NSC – Marking Guidelines  A serial connection using only one line is asynchronous because there is no additional clock line to synchronise exactly when data is sent or that both sides are running at the same speed. As computers rely on everything to be synchronised, this can present problems when two systems with different clocks try to communicate.  To get around this, asynchronous serial connections add extra start and stop bits to help the receiver synchronise the data as it arrives.  By adding an additional synchronising clock line this can hold both sides perfectly synchronised, called CLK or SCK.  The side generating the clock is called the master and the other side is called the slave.  The master sends data to the slave on the data line and if the slave needs to send a signal in response back the master first sends a number of clock pulses which are pre-arranged, and then the slave sends the data on a third line called MISO. 6.6.4 SPI supports higher speed full-duplex communication  SPI draws little power  SPI can operate at extremely high speeds (2) 6.7 6.7.1 Looping is when a task is repeated  over and over until the condition is true.  (2) 6.7.2 A conditional statement is a mechanism that allows for conditional execution of instructions  based upon the outcome of a conditional statement,  which can either be true or false.  (3) Copyright reserved Please turn over ### Page 16 Downloaded from hlayiso.com Electrical Technology: Digital Electronics 16 DBE/November 2022 NSC – Marking Guidelines 6.8 Start Green On Red Off Arrive? Depart? No No Yes Yes Invrease Var A  Decrease Var A   Green On Var A Red Off No   Yes  No Red On Depart? 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