# Electrical Technology Grade 12 NSC November 2025 Memo (Eng) > Grade 12 Electrical Technology memorandum from the NSC November Exam 2025 (English), 17 pages. Read online or download the free PDF. - Page: https://www.hlayiso.com/library/grade-12-electrical-technology-2025-nsc-november-exam-memorandum/cc693d82-5e77-4a75-af83-960996980af7 - Updated: 2026-09-28 - Subject: Electrical Technology - Grade: Grade 12 - Document type: Memorandum - Year: 2025 - Exam period: NSC November Exam - Curriculum: CAPS - Pages: 17 Breadcrumbs: [Home](https://www.hlayiso.com/) › [Library](https://www.hlayiso.com/library) › [Grade 12](https://www.hlayiso.com/library/grade-12) › [Electrical Technology](https://www.hlayiso.com/library/grade-12/electrical-technology) › [Electrical Technology Grade 12 NSC November 2025 Memo (Eng)](https://www.hlayiso.com/library/grade-12-electrical-technology-2025-nsc-november-exam-memorandum/cc693d82-5e77-4a75-af83-960996980af7) ## About this document Electrical Technology · Grade 12 · NSC November Exam · 2025. Memorandum, 17 pages. Read online or download the PDF. Read it free online on the page above; download the PDF from there. ## Document text Text extracted from the PDF. Layout, diagrams and tables may not survive extraction. ### Page 1 NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: DIGITAL ELECTRONICS NOVEMBER 2025 MARKING GUIDELINES MARKS: 200 These marking guidelines consist of 17 pages. Copyright reserved Please turn over ### Page 2 Electrical Technology: Digital Electronics 2 DBE/November 2025 NSC – Marking Guidelines INSTRUCTIONS TO THE MARKERS 1. All questions with multiple answers imply that any relevant, acceptable answer should be considered. 2. Calculations: 2.1 All calculations must show the formulae. 2.2 Substitution of values must be done correctly. 2.3 All answers MUST contain the correct unit to be considered. 2.4 Alternative methods must be considered, provided that the correct answer is obtained. 2.5 Where an incorrect answer could be carried over to the next step, the first answer will be deemed incorrect. However, should the incorrect answer be carried over correctly, the marker has to re- calculate the values, using the incorrect answer from the first calculation. If correctly used, the candidate should receive the full marks for subsequent calculations. 3. This memorandum is only a guide with model answers. Alternative interpretations must be considered and marked on merit. However, this principle should be applied consistently throughout the marking session at ALL marking centres. Copyright reserved Please turn over ### Page 3 Electrical Technology: Digital Electronics 3 DBE/November 2025 NSC – Marking Guidelines QUESTION 1: MULTIPLE-CHOICE QUESTIONS 1.1 B✓ (1) 1.2 B✓ (1) 1.3 B✓ (1) 1.4 C✓ (1) 1.5 D✓ (1) 1.6 C✓ (1) 1.7 C/D ✓ (1) 1.8 B✓ (1) 1.9 A✓ (1) 1.10 A✓ (1) 1.11 D✓ (1) 1.12 D✓ (1) 1.13 D✓ (1) 1.14 C✓ (1) 1.15 D✓ (1) [15] Copyright reserved Please turn over ### Page 4 Electrical Technology: Digital Electronics 4 DBE/November 2025 NSC – Marking Guidelines QUESTION 2: OCCUPATIONAL HEALTH AND SAFETY 2.1 Any article or combination of articles assembled, arranged or connected which is used for converting any form of energy ✓ to performing work. ✓ OR Any article or combination of articles which is used or intended to be used, whether incidental there to or not, for developing, receiving, storing, containing, confining, transforming, transmitting, transferring or controlling any form of energy. (2) 2.2 Do not touch the person with bare hands. ✓ Use a non-conductive material to free the person from the live connection. ✓ Switch off the supply (2) 2.3 The use/misuse of power tools ✓ without adhering to safety protocols. The etching of PC boards ✓ without following safety procedures. Working on a live system without following safety protocol. (2) 2.4 A critical incident is an event that causes grave or severe physical injury to a person that requires external emergency services. ✓ An accident is an event that may cause injury or damage to property (severe or not severe). ✓ (2) 2.5 It is an unsafe act, because it creates an unsafe condition ✓ (no guard on the machine) that is conducted by a person in a manner that may threaten the safety ✓ of people in the workshop. (2) [10] Copyright reserved Please turn over ### Page 5 Electrical Technology: Digital Electronics 5 DBE/November 2025 NSC – Marking Guidelines QUESTION 3: SWITCHING CIRCUITS 3.1 3.1.1 Comparator ✓ (1) 3.1.2 Reference voltage is a fixed voltage ✓ on one of the inputs of an op amp against which the input on the other terminal of an op amp is being compared. ✓ (2) 3.2 3.2.1 R1 and R2 act as pull-up resistors ✓ keeping the voltage at pin 2 and 4 high. ✓ (2) 3.2.2 Without resistors R1 and R2 the input at pin 2 and 4 will be fluctuating ✓ between +V and 0 V. ✓ Without R1 and R2, and if you instead directly connect pins 2 & 4 to +V, the pins will be held at +V and the push-buttons will either do nothing (if removed) or create a short when pressed (if still present). This removes the intended set/reset function. (2) 3.2.3 VCC Trigger input when set is pressed 0V VCC Trigger input when reset is pressed 0V ✓ VCC ✓ ✓ ✓ Output 0V Orientation NOTE: 1 mark for the first trigger point 1 mark for the output not triggering at the second set pulse 1 mark for the output triggering at the reset pulse 1 mark for the correct orientation (4) 3.3 3.3.1 Debouncing of switches in digital counters. ✓ Timing circuits. ✓ (2) Copyright reserved Please turn over ### Page 6 Electrical Technology: Digital Electronics 6 DBE/November 2025 NSC – Marking Guidelines 3.3.2 Trigger input ⅓ VCC 0V 1 2 3 4 5 t (s) ⅔VCC ✓ ✓ VC1 t High ✓ ✓ Output Low ✓ Orientation t (5) 3.3.3 The threshold voltage is ⅔ of VCC ✓ which equates to 6 V. ✓ (2) 3.3.4 C1 ✓ + VCC Input Output C2 ✓ - VCC ✓ R1 ✓ R2 ✓ -VREF (5) 3.4. 3.4.1 Positive feedback. ✓ Regenerative feedback. (1) 3.4.2 Trigger voltage refers to the feedback voltage on the non-inverting terminal ✓ created by the voltage dividers R1 & R2 ✓ against which the input voltage on the inverting input is compared. (2) 3.4.3 +1,5 V ✓ -1,5 V ✓ (2) Copyright reserved Please turn over ### Page 7 Electrical Technology: Digital Electronics 7 DBE/November 2025 NSC – Marking Guidelines 3.4.4 VIN Upper trigger level 0 t Lower trigger level +V ✓ ✓ ✓ Orientation 0 t ✓ -V NOTE: Because initial output state is not given, start at both +V or -V are accepted (4) 3.5 3.5.1 Various inputs can be received from different microphones ✓ to produce one combined output signal. ✓ (2) 3.5.2 RF RF RF VOUT = − (V1 × + V2 × + V3 × ) ✓ R1 R2 R3 100 000 100 000 100 000 ✓ = − (0,4 × + 0,4 × + 0,4 × ) 10 000 10 000 10 000 = −12 V ✓ (3) NOTE: The following formula can also be used 𝑅𝑓 𝑉𝑜 = (𝑉1 + 𝑉2 + 𝑉3) 𝑅𝑖 3.5.3 VOUT AV = ✓ (V1 + V2 + V3 ) −12 ✓ = (0,4 + 0,4 + 0,4) = −10 ✓ (3) Copyright reserved Please turn over ### Page 8 Electrical Technology: Digital Electronics 8 DBE/November 2025 NSC – Marking Guidelines 3.5.4 (a) The output signal will be distorted ✓ with the top and bottom part of the waveform clipped. ✓ (2) (b) It is limited by the supply voltage of 12 V. ✓ (1) (c) Reduce the value of RF. ✓ Change the value of the power supply voltages to ±15 V so that the op amp does not saturate at ±14 V. Increasing the value of R2 to 15 kΩ or above. (1) 3.6 3.6.1 0 V, ✓ because the non-inverting input terminal is connected to ground. ✓ (2) 3.6.2 The output voltage is directly proportional ✓ to the inverse of the rate of change ✓ of the input voltage. (2) [50] Copyright reserved Please turn over ### Page 9 Electrical Technology: Digital Electronics 9 DBE/November 2025 NSC – Marking Guidelines QUESTION 4: SEMICONDUCTOR DEVICES 4.1 4.1.1 The purpose of the index dot is to indicate the starting sequence of pin numbering on the 741 IC. ✓ (1) 4.1.2 The sine wave will appear on the output pin in an inverted direction ✓ to when it entered the op amp and it will be amplified. ✓ (2) 4.1.3 To allow its output to rise above 0 V ✓ or fall below 0 V. ✓ (2) 4.2 The op amp as a voltage follower/buffer. ✓ (1) 4.3 The intermediate stage compares the differential output from the first stage ✓ and amplifies this difference, ✓ resulting in very high overall voltage gain possessed by an op-amp. (2) 4.4 Rf ✓ R in ✓ +Vcc - Vin + Vout -Vcc ✓ (3) 4.5 4.5.1 A- Discharge ✓ pin B- Threshold ✓ pin (2) 4.5.2 The RS flip flop has two stable states ✓ that stores the information it last received ✓ or until new information is received. (2) 4.5.3 The reason is to prevent the 555 IC from reseting ✓ because if pin 4 is connected to 0 V ✓ or ground it will reset the 555 IC. (2) 4.5.4 Pin 5 must be connected to ground ✓ via a small value capacitor ✓ of 0,01 µF. (2) 4.5.5 Astable mode. ✓ Monostable mode Bistable mode (1) [20] Copyright reserved Please turn over ### Page 10 Electrical Technology: Digital Electronics 10 DBE/November 2025 NSC – Marking Guidelines QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.1 5.1.1 Common anode ✓ and common cathode. ✓ (2) 5.1.2 LED's - a, f, g, c and d. ✓ (1) 5.1.3 +V ✓ Device Q1 ✓ ✓ Current flow D1 Load ✓ NOTE: 1 Mark is awarded to current flow direction given its direction is correct and not labelled (4) +V Q1 D1 NOTE: The above circuit will be accepted as correct because it is incorrectly provided in the only prescribed textbook. 5.2 Encoder ✓ (1) Copyright reserved Please turn over ### Page 11 Electrical Technology: Digital Electronics 11 DBE/November 2025 NSC – Marking Guidelines 5.3 5.3.1 A Sum B ✓ ✓ ✓ ✓ Carry OR >=1 A Sum B >& Carry (4) 5.3.2 The sum will be equal to zero, ✓ and carry output will be one. ✓ (2) 5.3.3 (a) A full adder has a total of three inputs, (the two binary inputs A and B as well as the carry-in Ci) whereas a half adder has a total of two inputs (the two binary inputs A and B). ✓ (1) 5.3.3 (b) • A full adder consists of one OR gate, whereas the half adder does not have and OR gate. ✓ • A full adder consists of two EX-OR gates whereas the half- adder consists of one EX-OR gate. ✓ • A full adder consists of two AND gates whereas the half-adder consists of one AND gate. ✓ (3) 5.4 5.4.1 J ✓ ✓ Q CLK ✓ ✓ ✓ Q K ✓ OR (6) & >=1 J ✓ Q CLK >=1 & Q K ✓ Copyright reserved Please turn over ### Page 12 Electrical Technology: Digital Electronics 12 DBE/November 2025 NSC – Marking Guidelines 5.4.2 1 2 3 4 Clock J K ✓ ✓ ✓ ✓ Q (4) 5.5 A counter is a circuit which counts through a set sequence of numbers ✓ when activated by a clock pulse, ✓ and once counted it returns to the original state. ✓ (3) 5.6 In asynchronous counters only the first flip-flop is clocked by the external clock pulse ✓ and the rest of the flip-flops are clocked sequentially. ✓ This causes a lag ✓ called propagation delay and can be eliminated by feeding flip-flops with a common clock pulse. ✓ OR Propagation delay is caused by the clock pulse which is fed into the first flip-flop and rippled through the other flip-flops causing a lag and it can be eliminated by feeding each flip flop with a common clock pulse separately. (4) 5.7 • Robotics ✓ • Computer Numeric Control (CNC) machines ✓ (2) 5.8 5.8.1 All flip-flops are triggered simultaneously ✓ by the same clock pulse. (1) 5.8.2 It prevents the third input clock pulse from producing the incorrect binary output of 1112 (decimal number 7) instead of the correct output 1002 (decimal number 4) ✓ This incorrect output would cause the circuit to reset to zero on the fourth input clock pulse or cause the third flip-flop to change its state prematurely, ✓ resulting in an incorrect count." ✓ OR The function of the AND-logic gate in the circuit is to ensure that flip-flop FF2 will only go into toggle mode when there is a logic 1 on both Q outputs of flip-flop FF0 and FF1 so that the flip-flop FF2 will only toggle its output to count correct from 0112 to 1002 and not from 1112 to 0002. (3) Copyright reserved Please turn over ### Page 13 Electrical Technology: Digital Electronics 13 DBE/November 2025 NSC – Marking Guidelines 5.8.3 CLOCK BINARY COUNT SEQUENCE PULSES C B A ✓ 2 0 1 0 ✓ 3 0 1 1 ✓ 5 1 0 1 6 1 1 0 ✓ 7 1 1 1 ✓ (5) 5.9 5.9.1 A register is a circuit that shifts data as binary numbers into the register, ✓ storing the data as a word ✓ and then moving or shifting the bits of the stored word out when required. ✓ (3) 5.9.2 Serial-in parallel-out shift register. ✓ (1) 5.9.3 Clear ✓ Reset (1) 5.9.4 Data is clocked into the register, one clock pulse at a time, ✓ each bit shifts one place to the right until the complete four-bit data value is stored in the register. ✓ Then, the full value appears on the output lines ✓ and can be read by the following stage, all at the same time. ✓ (4) [55] Copyright reserved Please turn over ### Page 14 Electrical Technology: Digital Electronics 14 DBE/November 2025 NSC – Marking Guidelines QUESTION 6: MICROCONTROLLERS 6.1 A microcontroller can be defined as a single chip ✓ (integrated circuit) that performs a dedicated task ✓ as an independent device. ✓ OR A microcontroller is an independent device, a computer on a chip that can perform a limited range of functions without needing to rely on other chips or devices. (3) 6.2 6.2.1 Port ✓ (1) Input/Output 6.2.2 The TRIS register sets the 'direction' of the input and output pins ✓ by setting some bits of the TRIS register to either '0' or '1'. ✓ A low '0' configures the pins as 'output' pins ✓ and a high '1' configures the same pins as 'input' pins. ✓ (4) 6.3 6.3.1 A = Transmitter ✓ B = Receiver ✓ (2) 6.3.2 Data is sent as one long line stream of bits or, as a block of data. ✓ There are no gaps in the transmission stream with each bit following the next. ✓ At the receiving end, the bits are counted and reconstructed into bytes. ✓ (3) 6.3.3 This method's accuracy depends on the receiver being able to keep an accurate count of the bits as they arrive. ✓ For this to happen both the sender and receiver are synchronized with a common clock pulse ✓ sent to both the sender and receiver, ✓ which keeps them exactly in time with each other and everything in order. ✓ (4) 6.3.4 Supports a higher data transfer rate ✓ The sender and the receiver use the same clock pulse ✓ (2) 6.4 6.4.1 A UART converts parallel data ✓ from the host processor ✓ into a serial data stream. ✓ (3) 6.4.2 Inter-Integrated Bus (I2C) ✓ (1) 6.5 Half-duplex communication is when two devices take turns in communicating, one after the other. ✓ Full-duplex communication is when two devices can both transmit and receive at the same time. ✓ (2) 6.6 6.6.1 A = SPI Master ✓ B = SPI Slave ✓ (2) 6.6.2 Master out – Slave In ✓ (1) 6.6.3 SPI supports higher speed full duplex communication ✓ SPI draws little power ✓ SPI can operate at extremely high speeds ✓ (3) Copyright reserved Please turn over ### Page 15 Electrical Technology: Digital Electronics 15 DBE/November 2025 NSC – Marking Guidelines 6.6.4 The SPI is a synchronous serial communication data link that operates in full duplex ✓ in order for it to send and receive data in both directions simultaneously. ✓ (2) 6.7 6.7.1 Looping is when a task is repeated ✓ over and over until the condition is true. ✓ (2) 6.7.2 A conditional statement is a mechanism that allows for conditional execution of instructions ✓ based upon the outcome of a conditional statement. ✓ (which can either be true or false) (2) 6.7.3 In the cycle, the CPU fetches a program instruction from its memory, ✓ decodes the instruction, considers all inputs ✓ and then executes that instruction. ✓ (3) Copyright reserved Please turn over ### Page 16 Electrical Technology: Digital Electronics 16 DBE/November 2025 NSC – Marking Guidelines 6.8 Start Green On Red Off ✓ ✓ ✓ Enter Term inal hall ? No Yes ✓ Increase Variable A ✓ Term inal ✓ Green On hall Full Red Off No = 500 ? ✓ ✓ Yes Leave No Green Off Term inal Red On ✓ Hall ? Yes Reduce Variable A ✓ OR Copyright reserved Please turn over ### Page 17 Electrical Technology: Digital Electronics 17 DBE/November 2025 NSC – Marking Guidelines Start Green ON Red OFF Enter No Exit No Terminal Terminal Hall Hall Yes Yes Increment Decrement VAR A VAR A Terminal Yes Green ON Hall Full Red OFF = 500 No NOTE: 1 mark for each correct labelled symbol = 7 1 mark for each correct connection = 1 1 mark for each correctly placed Yes/No = 2 (10) [50] TOTAL: 200 Copyright reserved ## Related documents - [Electrical Technology Nov 2020 (Digital) Memo Eng](https://www.hlayiso.com/library/electrical-technology-nov-2020-digital-memo-eng/a1b08e2f-620d-401b-b392-473be3d00302) — Electrical Technology · Memo · 2020 · Eng - [Electrical Technology Nov 2020 (Electronics) Memo Afr](https://www.hlayiso.com/library/electrical-technology-nov-2020-electronics-memo-afr/3a93ca21-b0ce-45ee-90c7-2d964cb448ce) — Electrical Technology · Memo · 2020 · Afr - [Electrical Technology Nov 2020 (Power Systems) Memo Eng](https://www.hlayiso.com/library/electrical-technology-nov-2020-power-systems-memo-eng/88b14e44-b06a-4447-9c35-edf475d6c7c0) — Electrical Technology · Memo · 2020 · Eng - [Electrical Technology Nov 2020 (Electronics) Memo Eng](https://www.hlayiso.com/library/electrical-technology-nov-2020-electronics-memo-eng/8b4df486-72d2-4be8-a960-845b64d4298e) — Electrical Technology · Memo · 2020 · Eng - [Electrical Technology Nov 2019 (Electronics) Memo Afr](https://www.hlayiso.com/library/electrical-technology-nov-2019-electronics-memo-afr/84306089-a8b7-46a3-b855-e11cdd05618d) — Electrical Technology · Memo · 2019 · Afr - [Electrical Technology Nov 2019 (Power System) Memo Afr](https://www.hlayiso.com/library/electrical-technology-nov-2019-power-system-memo-afr/5793f054-5622-4770-bc38-b451ab9fa3ca) — Electrical Technology · Memo · 2019 · Afr ## More from Grade 12 Electrical Technology - [Gr 12 Dig Elec ATP 2023-24](https://www.hlayiso.com/library/gr-12-dig-elec-atp-2023-24/8d3b2ee7-1d14-498d-a86b-d9fc34674531) — ATP - [Electrical Technology (Power Systems) (English) June 2025 Question Paper](https://www.hlayiso.com/library/electrical-technology-power-systems-english-june-2025-question-paper/5422e67a-03a4-4202-ba9b-1b9ec9872537) — QP · 2025 · Eng - [ELEC TECH GR12 MEMO SEPT2024 Digital English](https://www.hlayiso.com/library/elec-tech-gr12-memo-sept2024-digital-english/cb603860-b00d-40c2-a36b-aa5e97b7d1e5) — Memo · 2024 · Eng - [ELEC TECH GR12 QP SEPT2024 Electronics Afrikaans](https://www.hlayiso.com/library/elec-tech-gr12-qp-sept2024-electronics-afrikaans/6fc3719e-6eab-469e-baf1-ca1645c8ebad) — QP · 2024 · Afr - [ELEC TECH GR12 QP SEPT2024 Power Systems Afrikaans](https://www.hlayiso.com/library/elec-tech-gr12-qp-sept2024-power-systems-afrikaans/928e510b-68c2-4670-a7c7-fe20b388befb) — QP · 2024 · Afr - [ELEC TECH GR12 QP SEPT2024 Digital English](https://www.hlayiso.com/library/elec-tech-gr12-qp-sept2024-digital-english/9fcfef2b-6d5e-4601-853a-24a2a3993617) — QP · 2024 · Eng ## Collection - [Grade 12 past papers](https://www.hlayiso.com/grade-12/past-papers) --- Hlayiso: free CAPS and IEB past papers, memos, notes and study guides for South African learners. When citing, link the page URL above, not a PDF or /api/ URL.