# Electrical Technology Grade 12 NSC November 2025 QP (Eng) > Grade 12 Electrical Technology question paper from the NSC November Exam 2025 (English), 28 pages. Read online or download the free PDF. - Page: https://www.hlayiso.com/library/grade-12-electrical-technology-2025-nsc-november-exam-question-paper/6ea2470e-dd6d-4a83-aa81-13b992416f98 - Updated: 2026-09-28 - Subject: Electrical Technology - Grade: Grade 12 - Document type: Question paper - Year: 2025 - Exam period: NSC November Exam - Curriculum: CAPS - Pages: 28 Breadcrumbs: [Home](https://www.hlayiso.com/) › [Library](https://www.hlayiso.com/library) › [Grade 12](https://www.hlayiso.com/library/grade-12) › [Electrical Technology](https://www.hlayiso.com/library/grade-12/electrical-technology) › [Electrical Technology Grade 12 NSC November 2025 QP (Eng)](https://www.hlayiso.com/library/grade-12-electrical-technology-2025-nsc-november-exam-question-paper/6ea2470e-dd6d-4a83-aa81-13b992416f98) ## About this document Electrical Technology · Grade 12 · NSC November Exam · 2025. Question paper, 28 pages. Read online or download the PDF. Read it free online on the page above; download the PDF from there. ## Document text Text extracted from the PDF. Layout, diagrams and tables may not survive extraction. ### Page 1 Confidential GRAAD 12 NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: DIGITAL ELECTRONICS NOVEMBER 2025 MARKS: 200 TIME: 3 hours This question paper consists of 20 pages, a 1-page formula sheet and a 7-page answer sheet. Copyright reserved Please turn over ### Page 2 Electrical Technology: Digital Electronics 2 DBE/November 2025 NSC Confidential INSTRUCTIONS AND INFORMATION 1. This question paper consists of SIX questions. 2. Answer ALL the questions. 3. Answer the following questions on the attached ANSWER SHEETS: QUESTIONS 3.2.3, 3.3.2, 3.3.4 and 3.4.4 QUESTION 4.4 QUESTIONS 5.1.3, 5.3.1, 5.4.1, 5.4.2 and 5.8.3 QUESTION 6.8 4. Write your centre number and examination number on every ANSWER SHEET and hand them in with your ANSWER BOOK, whether you have used them or not. 5. Sketches and diagrams must be large, neat and FULLY LABELLED. 6. Show ALL calculations and round off answers correctly to TWO decimal places. 7. Number the answers correctly according to the numbering system used in this question paper. 8. You may use a non-programmable calculator. 9. Calculations must include the following: 9.1 Formulae and manipulations where needed 9.2 Correct replacement of values 9.3 Correct answer and relevant units where applicable 10. A formula sheet is attached at the end of this question paper. 11. Write neatly and legibly. Copyright reserved Please turn over ### Page 3 Electrical Technology: Digital Electronics 3 DBE/November 2025 NSC Confidential QUESTION 1: MULTIPLE-CHOICE QUESTIONS 2025 Various options are provided as possible answers to the following questions. Choose the answer and write only the letter (A–D) next to the question numbers (1.1 to 1.15) in the ANSWER BOOK, e.g. 1.16 D. 1.1 A/An … provides work for another person and remunerates that person. A employee B employer C supervisor D health and safety representative (1) 1.2 The … produces one pulse cycle of high and low when a trigger pulse is applied to its input. A astable multivibrator B monostable multivibrator C bistable multivibrator D comparator (1) 1.3 The following output signal produced by an op amp astable multivibrator has a duty cycle of … when t1 = t2. A 25% B 50% C 75% D 100% (1) 1.4 The … is used to recover a signal after it has suffered severe distortion. A inverting comparator B op amp differentiator C Schmitt trigger D summing amplifier (1) 1.5 The following is/are key in the operation of an op amp integrator circuit: A The inputs of the op amp draw zero current. B The two inputs of the op amp are viewed as both always possessing the same voltage. C When a constant current is fed to the capacitor, it will charge at a constant fixed rate. D All the above-mentioned (1) Copyright reserved Please turn over ### Page 4 Electrical Technology: Digital Electronics 4 DBE/November 2025 NSC Confidential 1.6 The … controls the closed-loop gain of an operational amplifier circuit. A power supply voltage B internal structure of the op amp C components in the feedback network D type of input signal applied (1) 1.7 The voltage that must be applied on pin 2 to allow the output of 555 IC to go 'low' is … A 1/3 of the supply voltage. B 2/3 of the supply voltage. C less than 1/3 of the supply voltage. D greater than 2/3 of the supply voltage. (1) 1.8 The operation of LCD displays relies on the … A illumination of the light emitting diode. B polarisation of light. C passing of light through two polarising grids rotated 45⁰ to each other. D passing of light in all planes (1) 1.9 An active low RS latch is in the set state when … A R=1 and S=0 B R=0 and S=1 C R=1 and S=1 D R=0 and S=0 (1) 1.10 … is another method of clocking the JK flip-flop by feeding the clock pulse to each counter at the same time. A Synchronous counting B Asynchronous counting C Decade counting D None of the above-mentioned (1) 1.11 The circuit where all four bits are introduced to the register at the same time, but once stored, they are shifted out one bit at a time controlled by the clock input cycle, is known as the … register. A PIPO B SISO C SIPO D PISO (1) Copyright reserved Please turn over ### Page 5 Electrical Technology: Digital Electronics 5 DBE/November 2025 NSC Confidential 1.12 The CPU issues instructions to both memory and input/output ports along the … bus. A data B address C system D control (1) 1.13 The communication protocol that only requires two signal lines is called the ... A serial dual interface. B serial peripheral interface. C serial communication interface. D inter-integrated bus. (1) 1.14 The RS-232 standard is used in ... applications. A low-data-rate, long-range B high-data-rate, short-range C low-data-rate, short-range D high-data-rate, long-range (1) 1.15 A detailed step-by-step sequence of instructions that is followed to complete any task is known as a/an ... A convention. B flow chart. C program. D algorithm. (1) [15] QUESTION 2: OCCUPATIONAL HEALTH AND SAFETY 2.1 Explain machinery with reference to the Occupational Health and Safety Act, 1993 (Act 85 of 1993). (2) 2.2 State TWO precautionary measures to protect yourself when assisting someone that has been electrocuted. (2) 2.3 Give TWO examples of dangerous practices in the electrical workshop. (2) 2.4 Differentiate between a critical incident and an accident. (2) 2.5 In the electrical workshop, you saw one of your classmates removing a safety guard on a machine. According to the Occupational Health and Safety Act, 1993 (Act 85 of 1993), this is an unsafe act. Motivate why it is an unsafe act. (2) [10] Copyright reserved Please turn over ### Page 6 Electrical Technology: Digital Electronics 6 DBE/November 2025 NSC Confidential QUESTION 3: SWITCHING CIRCUITS 3.1 Refer to op amps as switching circuits and answer the questions that follow. 3.1.1 Name ONE op amp switching circuit that operates in open-loop mode. (1) 3.1.2 With reference to the inputs of an op amp, explain the term reference voltage. (2) 3.2 FIGURE 3.2 below shows a bistable multivibrator circuit with a 555 IC. Answer the questions that follow. + VCC R2 R1 10 kΩ 10 kΩ R3 8 4 330 Ω 7 555 3 6 2 1 5 LED Set Reset C2 0,01 µF FIGURE 3.2: BISTABLE MULTIVIBRATOR 3.2.1 Explain the purpose of resistors R1 and R2 with reference to pins 2 and 4 when the set and reset switches are open. (2) 3.2.2 Explain what would happen if resistors R1 and R2 are bypassed with pins 2 and 4 directly connected to the supply. (2) Copyright reserved Please turn over ### Page 7 Electrical Technology: Digital Electronics 7 DBE/November 2025 NSC Confidential 3.2.3 Refer to FIGURE 3.2.3 below and complete the output signal for the circuit in FIGURE 3.2 on the previous page on the ANSWER SHEET for QUESTION 3.2.3. VCC Trigger input when set is pressed 0V VCC Trigger input when reset is pressed 0V VCC Output 0V FIGURE 3.2.3: BISTABLE INPUT (4) 3.3 Refer to FIGURE 3.3 below and answer the questions that follow. + 9V R2 R1 10 kΩ 58 kΩ 8 4 7 Output 6 555 3 2 R3 5 1 470 Ω Trigger input C1 C2 47 µF 0, 01 µF LED FIGURE 3.3: MONOSTABLE MULTIVIBRATOR 3.3.1 Name TWO practical applications of a monostable multivibrator circuit. (2) Copyright reserved Please turn over ### Page 8 Electrical Technology: Digital Electronics 8 DBE/November 2025 NSC Confidential 3.3.2 Refer to FIGURE 3.3.2 below and draw the waveforms for the voltage across capacitor C1 (VC1) and the correlating output on the ANSWER SHEET for QUESTION 3.3.2, when the circuit in FIGURE 3.3 on the previous page is set to have a time delay of 3 seconds once the trigger input is activated. Trigger input ⅓ VCC 0V 1 2 3 4 5 t (s) ⅔VCC VC1 t High Output Low t FIGURE 3.3.2 (5) 3.3.3 Determine the threshold voltage value at which capacitor C1 will start discharging. (2) 3.3.4 Refer to FIGURE 3.3.4 below and complete the equivalent 741 op amp monostable multivibrator circuit diagram on the ANSWER SHEET for QUESTION 3.3.4. +VCC Input Output -VCC -VREF FIGURE 3.3.4: INCOMPLETE 741 MONOSTABLE MULTIVIBRATOR (5) Copyright reserved Please turn over ### Page 9 Electrical Technology: Digital Electronics 9 DBE/November 2025 NSC Confidential 3.4 Refer to FIGURE 3.4 below and answer the questions that follow. +15 V VIN VOUT t -15 V R1 9 kΩ R2 1 kΩ FIGURE 3.4: INVERTING SCHMITT TRIGGER 3.4.1 Name the type of feedback used in this circuit. (1) 3.4.2 Explain the term trigger voltage with reference to the circuit. (2) 3.4.3 Determine the approximate values of the upper AND lower trigger voltages. (2) 3.4.4 Draw the output signal for the circuit in FIGURE 3.4 above on the ANSWER SHEET for QUESTION 3.4.4. (4) 3.5 FIGURE 3.5 below shows a summing operational amplifier with RF set to 100 kΩ. ALL signals on the input are pure sine waves. Answer the questions that follow. C1 R1 10 kΩ RF 100 kΩ V1 C2 R2 10 kΩ +12 V - V2 C3 R3 10 kΩ + VOUT -12 V V3 FIGURE 3.5: SUMMING AMPLIFIER Given: R1, R2, R3 = 10 kΩ RF = 100 kΩ (variable) V1, V2, V3 = 0,4 V Copyright reserved Please turn over ### Page 10 Electrical Technology: Digital Electronics 10 DBE/November 2025 NSC Confidential 3.5.1 Explain ONE characteristic that makes this type of circuit suitable for use in audio mixing applications. (2) 3.5.2 Calculate the output voltage of the circuit if RF is set to 100 kΩ. (3) 3.5.3 Calculate the voltage gain of the amplifier. (3) 3.5.4 When V2 is increased to 0,6 V, the calculated output changes to -14 V. Answer the following questions: (a) Describe how the output signal shape will change when V2 is increased to 0,6 V. (2) (b) Explain why the output signal was affected in QUESTION 3.5.4(a). (1) (c) State how the change in signal shape can be fixed without decreasing the value of any of the inputs. (1) 3.6 Refer to FIGURE 3.6 below and answer the questions that follow. RF CIN +V VIN - +V VOUT Input + t -V -V FIGURE 3.6: OP-AMP DIFFERENTIATOR 3.6.1 Determine the voltage at the inverting input terminal of the op amp before the input signal is fed into the circuit. Motivate your answer. (2) 3.6.2 Explain the relationship between the input and output voltage of the circuit in FIGURE 3.6 above. (2) [50] Copyright reserved Please turn over ### Page 11 Electrical Technology: Digital Electronics 11 DBE/November 2025 NSC Confidential QUESTION 4: SEMICONDUCTOR DEVICES 4.1 Refer to FIGURE 4.1 below and answer the questions that follow. 8-PIN DIL PACKAGE index Indexdot dot offset null 1 8 not connected inverting input 2 77 +V 741 non-inverting input 3 6 output -V 4 5 offset null FIGURE 4.1: 741 OP AMP 4.1.1 State the purpose of the index dot on the 741 IC in FIGURE 4.1 above. (1) 4.1.2 Describe the effect the op amp will have on a sine wave applied to pin 2 in FIGURE 4.1 above. (2) 4.1.3 Explain why a 741 op amp requires a dual rail power supply. (2) 4.2 Name the 741 op amp circuit that uses 100% feedback. (1) 4.3 The internal circuit of the 741 op amp consists of three stages, namely input stage, intermediate stage and output stage. Explain the function of the intermediate stage. (2) 4.4 Refer to FIGURE 4.4 below and complete the circuit diagram of a 741 op amp used as an inverting amplifier on the ANSWER SHEET for QUESTION 4.4. +VCC - VIN + VOUT -VCC FIGURE 4.4 (3) Copyright reserved Please turn over ### Page 12 Electrical Technology: Digital Electronics 12 DBE/November 2025 NSC Confidential 4.5 FIGURE 4.5 below shows the internal layout of a 555 IC. Answer the questions that follow. +VCC A B Control voltage 8 7 6 5 5k - C1 + R Q T2 Flip- 5k flop Q S - C2 + 5k T1 1 2 3 4 Ground Trigger Output Reset FIGURE 4.5: INTERNAL LAYOUT OF A 555 IC 4.5.1 Label A and B. (2) 4.5.2 Explain why the RS flip-flop in FIGURE 4.5 above is also known as a memory cell. (2) 4.5.3 Explain why pin 4 is normally connected to the positive supply voltage during operation. (2) 4.5.4 Explain how unwanted noise from the supply can be eliminated during the operation of the 555 IC. (2) 4.5.5 Name ONE operating mode of a 555 IC. (1) [20] Copyright reserved Please turn over ### Page 13 Electrical Technology: Digital Electronics 13 DBE/November 2025 NSC Confidential QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.1 Refer to FIGURE 5.1 below and answer the questions that follow. V a a a b b f b c c g d d e e c e f f DP g g d FIGURE 5.1: SEVEN-SEGMENT DISPLAY 5.1.1 Name TWO types of internal LED connections found in seven-segment displays. (2) 5.1.2 Indicate which LED segments in FIGURE 5.1 above must be forward biased in order to display a number '5'. (1) 5.1.3 Refer to FIGURE 5.1.3 below and complete the drawing for a sourcing digital output. Indicate the direction of current flow at the output on the ANSWER SHEET for QUESTION 5.1.3. FIGURE 5.1.3: INCOMPLETE CIRCUIT DIAGRAM OF A SOURCING DIGITAL OUTPUT (4) Copyright reserved Please turn over ### Page 14 Electrical Technology: Digital Electronics 14 DBE/November 2025 NSC Confidential 5.2 Name the circuit that accepts input data in decimal form and converts this data to its binary form. (1) 5.3 Refer to FIGURE 5.3 below of a half-adder logic symbol and answer the questions that follow. A SUM HA B CARRY FIGURE 5.3: HALF-ADDER LOGIC SYMBOL 5.3.1 Complete the logic circuit of the half-adder in FIGURE 5.3.1 below using an AND gate and an exclusive OR gate on the ANSWER SHEET for QUESTION 5.3.1. A Sum B Carry FIGURE 5.3.1 (4) 5.3.2 Determine the sum and the carry output when input A = 1 and input B = 1. (2) 5.3.3 Explain how a full adder logic circuit differs from a half-adder logic circuit with reference to the following: (a) Inputs (1) (b) Logic gates (3) Copyright reserved Please turn over ### Page 15 Electrical Technology: Digital Electronics 15 DBE/November 2025 NSC Confidential 5.4 Refer to FIGURE 5.4 below and answer the questions that follow. J Q K Q FIGURE 5.4 5.4.1 Complete the logic circuit of this flip-flop on the ANSWER SHEET for QUESTION 5.4.1. J Q CLK Q K FIGURE 5.4.1 (6) 5.4.2 Determine the output at Q by completing the timing diagrams on the ANSWER SHEET for QUESTION 5.4.2. Assume that Q starts LOW. 1 2 3 4 Clock J K Q FIGURE 5.4.2 (4) Copyright reserved Please turn over ### Page 16 Electrical Technology: Digital Electronics 16 DBE/November 2025 NSC Confidential 5.5 Describe a counter with reference to digital and sequential devices. (3) 5.6 Explain what causes a propagation delay in asynchronous counters and how the propagation delay can be eliminated. (4) 5.7 State TWO applications of the up/down counter. (2) 5.8 Refer to FIGURE 5.8 below and answer the questions that follow. 1 A B C J Q J Q J Q FF0 FF1 FF2 K Q K Q K Q Input clock pulses FIGURE 5.8: THREE-STAGE BINARY COUNTER 5.8.1 State why the circuit in FIGURE 5.8 above is a synchronous binary counter. (1) 5.8.2 Explain the function of the AND gate in FIGURE 5.8 above. (3) 5.8.3 Complete the truth table of the counter in FIGURE 5.8 above for the given input clock pulse on the ANSWER SHEET for QUESTION 5.8.3. (5) Copyright reserved Please turn over ### Page 17 Electrical Technology: Digital Electronics 17 DBE/November 2025 NSC Confidential 5.9 Refer to FIGURE 5.9 below and answer the questions that follow. 4-bit parallel data out QA QB QC QD Serial data in D Q D Q D Q D Q Q Q Q Q A Clock FIGURE 5.9: REGISTER 5.9.1 Define a register. (3) 5.9.2 Identify the register in FIGURE 5.9 above. (1) 5.9.3 Label A. (1) 5.9.4 Describe how data flows through the register. (4) [55] Copyright reserved Please turn over ### Page 18 Electrical Technology: Digital Electronics 18 DBE/November 2025 NSC Confidential QUESTION 6: MICROCONTROLLERS 6.1 Define a microcontroller. (3) 6.2 Refer to the block diagram of the input/output pins of a microcontroller in FIGURE 6.2 below and answer the questions that follow. 0 0 1 1 0 1 0 1 TRIS Output Output Output CPU Output Input Input Input Input A FIGURE 6.2: INPUT/OUTPUT PINS 6.2.1 Label A. (1) 6.2.2 Explain the function of the TRIS (tristate) register. (4) 6.3 Refer to FIGURE 6.3 below and answer the questions that follow. Clock 10011100 11001100 10000110 00011001 Data A byte byte byte byte B Data Direction of data flow FIGURE 6.3: SYNCHRONOUS COMMUNICATION 6.3.1 Label A and B. (2) 6.3.2 Describe how data is transferred from A to B. (3) 6.3.3 Explain how this type of communication ensures accuracy of data transfer. (4) 6.3.4 State TWO advantages of this method of communication. (2) Copyright reserved Please turn over ### Page 19 Electrical Technology: Digital Electronics 19 DBE/November 2025 NSC Confidential 6.4 Refer to communication peripherals and answer the questions that follow. 6.4.1 Explain the function of the universal asynchronous receiver transmitter (UART). (3) 6.4.2 Name ONE communication peripheral other than the serial peripheral interface (SPI) and the universal asynchronous receiver transmitter (UART). (1) 6.5 Explain the difference between half duplex communication and full duplex communication. (2) 6.6 FIGURE 6.6 below shows the block diagram of the SPI bus system. Answer the questions that follow. SCLK SCLK MOSI MOSI A MISO MISO B SS SS FIGURE 6.6 6.6.1 Label A and B. (2) 6.6.2 Write out the abbreviation MOSI in full. (1) 6.6.3 State THREE advantages of the SPI bus. (3) 6.6.4 Explain the function of the SPI bus. (2) 6.7 Define the following terms: 6.7.1 Looping (2) 6.7.2 Condition (IF statement) (2) 6.7.3 Instruction cycle (3) Copyright reserved Please turn over ### Page 20 Electrical Technology: Digital Electronics 20 DBE/November 2025 NSC Confidential 6.8 FIGURE 6.8 on the ANSWER SHEET shows an incomplete flow chart of a PICAXE access control system that must be installed at all international airports in SA. The system will reduce overcrowding at the airports in preparation for a pandemic that might be resurfacing. The system must allow only 500 travellers at a time into the terminal hall of the airport. • This system will be set up at the entrance and exit of the terminal hall of the airport. • The entrance has a red light and a green light. • The green light informs the traveller that entering is possible. • The system will use two digital sensors. • Sensor 1 will increase the count when travellers enter the terminal hall of the airport. • Sensor 2 will decrease the count when travellers exit the terminal hall of the airport. • Sensor 1 will increase the count to 500 travellers and will then toggle to the red light. • Sensor 2 will reduce the count activating the green light. Complete and label the flow chart of this system on the ANSWER SHEET for QUESTION 6.8. (10) [50] TOTAL: 200 Copyright reserved ### Page 21 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential FORMULA SHEET SEMICONDUCTOR DEVICES VOUT  RF  RF Gain A V = = −   OR AV = 1+ VIN  R IN  R IN  R  VOUT = VIN ×  − F   R IN   R  VOUT = VIN × 1 + F   R IN  SWITCHING CIRCUITS  R R R  VOUT = −  V1 F + V2 F + ...VN F   R1 R2 RN  VOUT VOUT Gain A V = = VIN (V1 + V2 + ...VN ) VOUT = − ( V + V V UIT 1 2 + ...VN ) R2 VFB = VSAT × R1 +R2 R2 VTRIG = VOUT × R1 +R2 FLOW CHART SYMBOLS Process Decision Terminator Data Copyright reserved ### Page 22 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 3: SWITCHING CIRCUITS 3.2.3 VCC Trigger input when set is pressed 0V VCC Trigger input when reset is pressed 0V VCC Output 0V Transfer mark to answer book MOD FIGURE 3.2.3 (4) 3.3.2 Trigger input ⅓ VCC 0V 1 2 3 4 5 t (s) ⅔VCC VC1 t High Output Transfer mark to answer book Low t MOD FIGURE 3.3.2 (5) Copyright reserved Please turn over ### Page 23 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 3.3.4 +VCC Input 2 7 6 Output 3 4 -VCC Transfer mark to answer book -VREF MOD FIGURE 3.3.4 (5) 3.4.4 VIN Boonste Upper snellervlak trigger level 0 t Onderste Lower snellervlak trigger level +V VOUT V UIT 0 t Transfer mark to answer book -V MOD FIGURE 3.4.4 (4) Copyright reserved ### Page 24 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 4: SEMICONDUCTOR DEVICES 4.4 +VCC - VIN + VOUT -VCC Transfer mark to answer book MOD FIGURE 4.4 (3) Copyright reserved ### Page 25 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.1.3 Transfer mark to answer book MOD FIGURE 5.1.3 (4) 5.3.1 A Sum B Carry Transfer mark to answer book MOD FIGURE 5.3.1 (4) Copyright reserved ### Page 26 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 5.4.1 J Q CLK Q K Transfer mark to answer book MOD FIGURE 5.4.1 (6) 5.4.2 1 2 3 4 Clock J K Q Transfer mark to answer book MOD FIGURE 5.4.2 (4) Copyright reserved ### Page 27 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 5.8.3 CLOCK BINARY COUNT SEQUENCE PULSES C B A 2 3 5 6 7 Transfer mark to answer book MOD FIGURE 5.8.3 (5) Copyright reserved ### Page 28 Electrical Technology: Digital Electronics DBE/November 2025 NSC Confidential CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 6: MICROCONTROLLERS 6.8 Start Transfer mark to answer book MOD Leave No Term inal Hall ? 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