Electrical Technology PAT GR 12 2019 (Digitals) Eng

Downloaded from hlayiso.com ELECTRICAL TECHNOLOGY – DIGITAL GUIDELINES FOR PRACTICAL ASSESSMENT TASKS GRADE 12 2019 These guidelines consist of 42 pages. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 2 DBE/PAT 2019 NSC TABLE OF CONTENTS 1. INTRODUCTION .................................................................................................................3 2. TEACHER GUIDELINES ........................................................................................................5 2.1 How to administer PATs ........................................................................................................5 2.2 How to mark/assess the PATs ...............................................................................................5 2.3 PAT assessment management plan........................................................................................5 2.4 Moderation of PATs ..............................................................................................................6 2.5 Absence/Non-submission of tasks .........................................................................................7 2.6 Simulations ...........................................................................................................................7 2.7 Projects ................................................................................................................................8 2.8 Working marks sheet ............................................................................................................9 3. LEARNER GUIDELINES ...................................................................................................... 10 3.1 Instructions to the learner ................................................................................................... 11 3.2 Declaration of authenticity (COMPULSORY) ......................................................................... 11 4. SIMULATIONS .................................................................................................................. 12 4.1 Simulation 1: 741 op amp and 555 IC ................................................................................... 12 4.2 Simulation 2: Bi-stable multivibrator and an LED sequencer ................................................. 17 4.3 Simulation 3: 741 op amp Schmidt trigger and summing amplifier circuit ............................. 22 4.4 Simulation 4: Connect a 7-segment display to a 4-bit BCD 7-segment display driver ............. 26 5. SECTION B – DESIGN AND MAKE ...................................................................................... 29 5.1 Design and Make: Part 1 ..................................................................................................... 30 5.2 Assessment of the Design and Make Phase: Part 1 ............................................................... 34 5.3 Design and Make: Part 2 ..................................................................................................... 36 5.4 Assessment of the Design and Make Phase: Part 2 .............................................................. 38 6. PROJECTS ........................................................................................................................ 39 6.1 Practical Project 1: Traffic light ............................................................................................ 39 6.2 Practical Project 2: Cellphone detector ................................................................................ 40 7. CONCLUSION ................................................................................................................... 42 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 3 DBE/PAT 2019 NSC 1. INTRODUCTION The 17 Curriculum and Assessment Policy Statements subjects which contain a practical component all include a practical assessment task (PAT). These subjects are: • AGRICULTURE: Agricultural Management Practices, Agricultural Technology • ARTS: Dance Studies, Design, Dramatic Arts, Music, Visual Arts • SCIENCES: Computer Applications Technology, Information Technology, Technical Sciences • SERVICES: Consumer Studies, Hospitality Studies, Tourism • TECHNOLOGY: Civil Technology, Electrical Technology, Mechanical Technology and Engineering Graphics and Design A practical assessment task (PAT) mark is a compulsory component of the final promotion mark for all candidates offering subjects that have a practical component and counts 25% (100 marks) of the end-of-the-year examination mark. The PAT is implemented across the first three terms of the school year. This is broken down into different phases or a series of smaller activities that make up the PAT. The PAT allows for learners to be assessed on a regular basis during the school year and it also allows for the assessment of skills that cannot be assessed in a written format, e.g. test or examination. It is therefore important that schools ensure that all learners complete the practical assessment tasks within the stipulated period to ensure that learners are resulted at the end of the school year. The planning and execution of the PAT differs from subject to subject. Practical assessment tasks are designed to develop and demonstrate a learner's ability to integrate a variety of skills in order to solve a problem. The PAT also makes use of a technological process to inform the learner what steps needs to be followed to derive a solution for the problem. The PAT consists of four or more simulations and a practical project. The teacher may choose any one of the practical projects and any four simulations available for power systems. The teacher must apply assessment on an ongoing basis at the same time that the learner is developing the required skills. Four simulations should be completed by the learners, in addition to the manufacturing of a practical project. The PAT incorporates all the skills the learner has developed throughout the year. The PAT ensures that all the different skills will be acquired by learners on completion of practical work, as well as the correct use of tools and instruments. Requirements for presentation A learner must present the following: • PAT file with all the evidence of simulations, design and prototyping. A copy of the PAT 2019 cover page. The relevant simulations and assessment sheets should be copied and handed to each learner to include in the file. • Practical project with: o Enclosure:  The file must include a design.  The enclosure and the design must match.  No cardboard boxes are allowed. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 4 DBE/PAT 2019 NSC  Plastic and metal enclosures are acceptable.  The enclosure should be accessible for scrutiny inside.  Lids that are secured with screws are preferred. o Circuit board:  The file should include the PCB design.  The PCB must be mounted inside the enclosure in such a manner that it can be removed for scrutiny.  Switches, potentiometers, connectors and other items must be mounted.  Wiring must be neat and bound/wrapped.  Wiring must be long enough to allow for the PCB to be removed and inspected with ease. o Logo and name:  The file should contain the logo and name design.  Logo and name must be prominent on the enclosure. The PAT will have a financial impact on the school's budget and school management teams are required to make provision to accommodate this particular expense. PAT components and other items must be acquired timeously, for use by the learners, before the end of the first term at the start of the academic year. It is the responsibility of the HOD to ensure that the teacher is progressing with the PAT from the start of the school year. Provincial departments are responsible for setting up moderation timetables and consequently PATs should be completed in time for moderation. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 5 DBE/PAT 2019 NSC 2. TEACHER GUIDELINES 2.1 How to administer PATs Teachers must ensure that learners complete the simulations required for each term. The project should be started in January in order to ensure its completion by August. In instances where formal assessments take place, the teacher has to assume the responsibility thereof. The PAT should be completed during the first three terms and must be ready at the start of PAT moderation. Teachers must make copies of the relevant simulations and hand it to learners at the beginning of each term. The PAT must not be allowed to leave the workshop and must be kept in a safe place at all times when learners are not working on it. The weightings of the PAT must be adhered to and teachers are not allowed to change weightings for the different sections. 2.2 How to mark/assess the PATs The PAT for Grade 12 will be set and assessed internally, but moderated externally. All formal assessment will be done by the teacher. The teacher is required to produce a working model and model answer file that sets the baseline for assessment at a Highly Competent Level for every project choice exercised by the learners. This file must include all the simulations with answers the teacher has done him/herself. The teacher will use the model answers and project to assess the simulations and projects of the learners. Once a facet sheet has been completed by the teacher, assessment will be deemed to be complete. No re-assessment will be done once the facet sheets have been completed and captured by the teacher. Learners must ensure that the work is done to the required standard before the teacher finally assesses the PAT during each stage of completion. 2.3 PAT assessment management plan The assessment plan for the PAT is as follows: TIME FRAME ACTIVITY RESPONSIBILITY Preparation for Teacher – Builds the models and works out the model answers PAT 2019 for the simulations for 2019. Identifies shortages in tools, equipment and consumable items for simulations that must be procured in 2019 SMT – Receives procurement requests from teachers and processes payments for the acquisition of required items January – Simulations 1 Teacher – Copies and hands out simulations March 2019 and 2 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday January 2019 PAT project – Teacher – Obtains quotations for PAT projects procurement Principal – Approves PAT procurement for PAT projects Teacher – Ensures that PAT projects are ordered and delivered HOD – Checks in on teacher to see if the process is adhered to Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 6 DBE/PAT 2019 NSC February 2019 PAT project – Teacher – Ensures that there is secure storage for PAT projects learners Teacher – Hands out and takes in PAT projects commence Teacher – Includes practical sessions for learners to complete with project the PAT project every week Learners – Commence with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis April – Moderation of District subject facilitator/subject specialist will visit the school June 2019 Simulations 1 and moderate Simulation 1 and 2 and 2 10% of learners' work is moderated April – Simulations 3 Teacher – Copies and hands out simulations June 2019 and 4 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday April – PAT project – Teacher – Ensures that there is secure storage for PAT projects June 2019 learners Teacher – Hands out and takes in PAT projects continue with Teacher – Includes practical sessions for learners to complete project the PAT project every week Learners – Continue with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis July holidays PAT Learners that are behind on the PAT are required to complete 2019 intervention the project during this holiday. July – Moderation of District subject facilitator/subject specialist will visit the school August 2019 Simulations 3 and moderate Simulations 3 and 4 – different learners from the and 4 previous term 10% of learners' work is moderated July – PAT project – Teacher – Ensures that there is secure storage for PAT projects August 2019 completion Teacher – Hands out and takes in PAT projects Teacher – Completes the PAT project with learners and compiles the PAT file Learners – Completes the PAT project and file HOD – Checks to see that 100% of the PAT files and projects are completed and assessed September – PAT PAT projects are moderated by subject facilitators/subject October 2019 moderation specialists from the province and learners are available to demonstrate skills 10% of learners are moderated randomly 2.4 Moderation of PATs Provincial moderation of each term's simulations will start as early as the following term. Simulations 1 and 2 should be moderated as soon as the second term starts. Similarly, Simulations 3 and 4 will be moderated in July. The project will, however, only be moderated on completion. During moderation of the PAT the learner's file and project must be presented to the moderator. The moderation process is as follows: • During moderation, learners are randomly selected to demonstrate the different simulations. All four simulations will be moderated. • The teacher is required to build an exemplar model for each project type chosen for the school. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 7 DBE/PAT 2019 NSC • This model must be on display during moderation. • The teacher's model forms the standard of the moderation at Level 4 (Highly Competent). • Level 5 assessments must exceed the model of the teacher in skill and finishing. • Learners who are moderated will have access to their files during moderation and may refer to the simulations they completed earlier in the year. • Learners may NOT ask assistance from other learners during moderation. • All projects and files must be on display for the moderator. • If a learner is unable to repeat the simulation or cannot produce a working circuit during moderation, marks will be deducted and circuits assessed as not being operational. • The moderator will randomly select no fewer than two projects (not simulations) and the learners involved will have to explain how the project was manufactured. • Where required, the moderator should be able to call on the learner to explain the function and principles of operation, and request the learner to exhibit the skills acquired through the simulations for moderation purposes. • On completion the moderator will, if needed, adjust the marks of the group upwards or downwards, depending on the outcome of moderation. • Normal examination protocols for appeals will be adhered to, if a dispute arises from adjustments made. 2.5 Absence/Non-submission of tasks The absence of a PAT mark in Electrical Technology without a valid reason: The learner will be given three weeks before the commencement of the final end-of-year examination to submit outstanding task. Should the learner fail to fulfil the outstanding PAT requirement, such a learner will be awarded a zero (0) for that PAT component. 2.6 Simulations Simulations are circuits, experiments and tests/tasks which the learner will have to build, test and measure and practically do as part of the development of practical skills. These skills have to be illustrated to the external moderator that visits the school at intervals during the school year. Teachers who make use of simulation programs on a computer may use it for the learners to practice on. However, it is required that the circuit be built using real components and that measurements be made with actual instruments for the purposes of assessment and moderation. The correct procedure for completing simulations is outlined below for teachers and school management teams who are responsible for the implementation of the PAT in Electrical Technology. STEP 1: The teacher will choose simulations from the provided examples. STEP 2: Compile a list of the components needed for every simulation. Add extra components as these items are very small and you will need extras, as these items get lost/damaged very easily when learners are working with it. STEP 3: Contact three different electronics component suppliers for comparative quotations. STEP 4: Submit the quotations to the SMT for approval and procurement of the items. STEP 5: Place the components in storage. Collate items for each simulation, thus making it easier to distribute and use during practical sessions. Ensure that different values of components do not mix, as this would lead to components being used incorrectly and this could damage the component and in extreme cases, the equipment used. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 8 DBE/PAT 2019 NSC STEP 6: Copy the relevant simulations and hand them out to learners at the start of the term. Teachers are allowed to adjust circuits and component values to suit their environment/ resource availability. Teachers are required to develop a set of model answers in the teacher's file. Moderators will use the teacher's model answers and artefacts when moderating. 2.7 Projects The projects are construction projects teachers can choose for their learners. These projects are based on proven circuits provided from schools and subject advisors. The projects are based on working prototypes and require careful construction in order for it to operate correctly. Projects are varied in cost and teachers must ensure that the projects chosen fall within the scope of the school's budget. Once the teacher has decided on a circuit, he/she must construct the prototype. Thereafter, copies of the provided circuit can be made and distributed to learners. They MUST redraw these circuits in their file correctly. The description of the operation of the circuits is NOT complete. It is required of learners to interrogate the function of the components in the provided circuit. They should elaborate on the purpose of components in the circuit. It is recommended that those learners investigate similar circuits available on the internet and in the school library or workshop reference books. Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 9 DBE/PAT 2019 NSC 2.8 Working marks sheet (A working Excel file is provided with this PAT.) PAT mark sheet Term 1 Term 2 Project Mark out of 100 Moderated Mark Total = Design Design Term 1 + Simulation Simulation Simulation Simulation and and Term 2 + 1 2 3 4 Make Make Project Part 1 Part 2 No. Name of Learner 40 40 40 40 70 20 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Total Average Teacher Name: Principal Name: Moderator Name: Signature: Signature: Signature: School Stamp Date: Date:_________________________ Date:__________________________ Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 10 NSC 3. LEARNER GUIDELINES PAT 2019 cover page (Place this page at the front of the PAT.) Department of Basic Education Grade 12 CAPS for Technical High Schools Practical Assessment Task – Electrical Technology Time allowed: Terms 1–3 (2019) Learner Name: Class: School: Specialisation: DIGITAL ELECTRONICS Complete FOUR simulations. Project (Write the name of the project): _____________________________ Evidence of moderation: NOTE: When the learner evidence (LE) selected has been moderated at school level, the table will contain evidence of moderation. Provincial moderators will sign the provincial moderation and only sign if re-moderation is needed. Moderation Signature Date Signature Date School-based Provincial moderation Re-moderation Mark allocation Moderated PAT Component Maximum Mark Learner Mark Mark Simulation 1 40 Simulation 2 40 Simulation 3 40 Simulation 4 40 Design and Make Project – Circuit 70 Design and Make Project – Enclosure 20 Total 250 Copyright reserved

Downloaded from hlayiso.com Electrical Technology 11 DBE/PAT 2019 NSC 3.1 Instructions to the learner • The PAT counts 25% of your final promotion mark. • All work produced by you must be your own effort. Group work and co-operative work are not allowed. • The PAT must be completed over three quarters. • The PAT file must contain four simulations and a practical project. • Calculations should be clear and include units. Calculations should be rounded off to TWO digits. SI units should be used. • Circuit diagrams can be hand-drawn or drawn on CAD. NO photocopies or scanned files are allowed. • Photos are allowed and can be in colour or greyscale. Scanned photos and photocopies are allowed. • Learners with identical photos will be penalised and receive zero (0) for that section. • This document must be placed inside your PAT file together with the other evidence. 3.2 Declaration of authenticity (COMPULSORY) Declaration: I _____ (Name) herewith declare that the work represented in this file is entirely my own effort. I understand that if proven otherwise, my final results may be withheld. _____ Signature of learner _____ Date Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 12 DBE/PAT 2019 NSC 4. SIMULATIONS 4.1 Simulation 1: 741 op amp and 555 IC Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.1.1 PURPOSE Construct a simple circuit using the 741 op amp to build a non-inverting amplifier and display the input/output waveforms on an oscilloscope. ACTIVITY 1A: Constructing a circuit using the 741 op amp 4.1.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x LM741 IC • Analogue/Digital oscilloscope • 1 x 1KΩ resistor • Function generator • 1 x 10 KΩ resistor • Variable DC power supply • Connecting wires • Wire-stripper • Side cutters 4.1.3 PROCEDURE (a) Construct the circuit as in FIGURE 1.1 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 13 DBE/PAT 2019 NSC FIGURE 1.1 (b) Connect the function generator between ground and Vin. (1) (c) Connect Channel 1 to the input and Channel 2 to the output. (d) Set the function generator to give a sine wave output. (e) Adjust the function generator to 1 000 Hz (1 kHz) at a voltage of 1 V peak. (f) Switch on the power to the circuit and observe the input and output waveforms. (g) Draw the input and output waveforms below. INPUT WAVEFORM (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 14 DBE/PAT 2019 NSC OUTPUT WAVEFORM (4) 4.1.4 QUESTIONS (a) Calculate the gain of the amplifier with the given resistor values. (3) (b) State how the gain of the amplifier will be affected if the feedback resistor is halved. (2) 4.1.5 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 3 (3) Subtotal: Activity 1A [21] ACTIVITY 1B: Constructing a circuit using the 555 IC 4.1.6 PURPOSE Construct a simple circuit using the 555 IC to build a clock pulse generator (astable multivibrator) and display the output waveforms on an oscilloscope. 4.1.7 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x 555 timer IC • Analogue/Digital oscilloscope • 1 x 220 Ω resistor • Function generator • 1 x LED • Variable DC power supply • 1 x 10 nF capacitor • Wire-stripper • 1 x 10 KΩ resistor • Side cutters • 1 x 100 KΩ pre-set POT • 1 x 10 µF (electrolytic capacitor 16 V) • Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 15 DBE/PAT 2019 NSC 4.1.8 PROCEDURE (a) Construct the circuit on the breadboard as in FIGURE 1.2 below. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) FIGURE 1.2 (b) Connect Channel 1 of the oscilloscope to the output. (c) Switch the power on to the circuit and observe the output waveform on the oscilloscope and the LED. (d) Draw the output waveform observed on the oscilloscope on the grid below. OUTPUT WAVEFORM (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 16 DBE/PAT 2019 NSC 4.1.9 QUESTIONS (a) List the components responsible for the frequency of the output. (3) (b) Calculate the charging time for the circuit using the given components. (3) 4.1.10 HOUSEKEEPING 1 2 3 The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. The learner failed to get The learner was able to The learner was able to the output wave on the set the oscilloscope and set the oscilloscope and oscilloscope. managed to get the output managed to get the output wave after the assistance wave without the from the teacher. assistance of the teacher. (6) Subtotal: Activity 1B [19] Subtotal: Activity 1A (21) Subtotal: Activity 1B (19) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 17 DBE/PAT 2019 NSC 4.2 Simulation 2: Bi-stable multivibrator and an LED sequencer Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.2.1 PURPOSE Construct a simple circuit using the 555 IC to build a bi-stable multivibrator and display output waveforms on an oscilloscope ACTIVITY 2A: Construct a circuit using the 555 IC. 4.2.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 2 x LEDs • Analogue/Digital oscilloscope • 2 x 470 Ω resistors • Function generator • 1 x 10 nF capacitor • Variable DC power supply • 2 x 47 KΩ resistor • Wire-stripper • 2 x N/O tactile pushbutton switches • Side cutters • 1 x 555 timer • Connecting wires 4.2.3 PROCEDURE (a) Connect the circuit on the breadboard as shown in FIGURE 2.1. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 18 DBE/PAT 2019 NSC FIGURE 2.1 (b) Connect Channel 1 of the oscilloscope to the output. (c) Switch on the power to the circuit and observe the output waveform on the oscilloscope. (d) Observe the state of both LEDs. LED 1 is _______ and LED 2 is ________. (2) (e) Now close only the SET switch and observe the state of both LEDs. LED 1 is _______ and LED 2 is ________. (2) (f) Now close only the RESET switch and observe the state of both LEDs. LED 1 is _______ and LED 2 is ________. (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 19 DBE/PAT 2019 NSC (g) Draw the inputs (set and reset) and output waveforms on the same axis. INPUT WAVEFORM AND OUTPUT WAVEFORM ________V/DIV ________µs/DIV (6) (h) CONCLUSION (2) Subtotal: Activity 2A [18] 4.2.4 PURPOSE Construct a simple circuit using the LED sequencer. Use a 4017B Johnson counter to light up 6 LEDs in sequence. ACTIVITY 2B: Construct a circuit using the 4017B IC. 4.2.5 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 4017 decade counter/divider • Analogue/Digital oscilloscope • 555 timer IC • Function generator • Ten-segment bar graph LED • Variable DC power supply • One SPST switch 1 • Wire-stripper • 6 volt battery • Side cutters • 10 kΩ resistor • 1 MΩ resistor • 0,1 µF capacitor • Coupling capacitor, 0,047 to 0,001 µF • 10 x 470 Ω resistors • Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 20 DBE/PAT 2019 NSC 4.2.5 PROCEDURE (a) Construct the circuit as in FIGURE 2.2 on the breadboard FIGURE 2.2 (b) Build the 555 timer (astable multivibrator) circuit to produce clock pulses and observe on the oscilloscope. 1 3 4 The learner was able to The learner was able to The learner was able to construct a minimum construct a part of the construct the timing part of the timing circuit timing circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. The learner failed to get The learner was able to The learner was able to the output wave on the set the oscilloscope and set the oscilloscope and oscilloscope. managed to get the managed to get the output wave after the output wave without the assistance from the assistance of the teacher. teacher. (8) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 21 DBE/PAT 2019 NSC (c) Draw the output waveform of the 555 on the grid below. OUTPUT WAVEFORM (2) (d) Build the Johnson counter and connect the output of the 555 timer to the clock pulse. The learner was able to The learner was able to The learner was able to construct a minimum construct a part of the construct the counter part of the counter counter circuit correctly circuit correctly without circuit correctly without without assistance. assistance. assistance. 1 3 5 (5) The learner did not do The learner did The learner did any housekeeping housekeeping after housekeeping without duties. being reminded. being reminded. 1 3 4 (4) (e) CONCLUSION (3) Subtotal: Activity 2B [22] Subtotal: Activity 2A (18) Subtotal: Activity 2B (22) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 22 DBE/PAT 2019 NSC 4.3 Simulation 3: 741 op amp Schmidt trigger and summing amplifier circuit Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.3.1 PURPOSE Construct a simple circuit using a 741 op amp to build a Schmidt trigger circuit and a summing amplifier circuit. Display the output waveforms on an oscilloscope. ACTIVITY 3A: Constructing a Schmidt trigger circuit using the 741 op amp 4.3.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x LM741 op amp • Analogue/Digital oscilloscope • 2 x 10 KΩ resistors • Function generator • 3 x 1 kΩ resistors • Variable DC power supply • 1 x 2k2 Ω resistor (pre-set POT) • Wire-stripper • 1 x 100 kΩ resistor • Side cutters • 1 x 1MΩ • 1 x LED • Connecting wires 4.3.3 PROCEDURE (a) Construct the circuit as in FIGURE 3.1 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) FIGURE 3.1 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 23 DBE/PAT 2019 NSC (b) Adjust the potentiometer, while observing the output voltage. The output switches to HIGH when Vin is ________V and to LOW when Vin is ________V. The hysteresis is _______V. (3) (c) Replace the 100 k resistor with 10 k. Adjust the input potentiometer slowly. (d) While watching the LED on the output, can you change the output of the comparator to adjust the brightness of the LED? _________. (1) The output now switches to HIGH when the input voltage is ______V and to LOW (1) at ________V. The hysteresis is ________V. (2) (e) Replace the hysteresis resistor with 1 M. The output now switches to HIGH at _________V and to a LOW at _____ V. (2) The hysteresis is ________V. (1) Remove the hysteresis resistor and adjust the potentiometer slowly. 4.3.4 CONCLUSION (3) 4.3.5 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 4 (4) Subtotal: Activity 3A [21] ACTIVITY 3B: Constructing a summing amplifier circuit using the 741 op amp 4.3.6 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 6 x 1k Ω resistors • Analogue/Digital oscilloscope • 4 x 10 kΩ resistors • Function generator • 1 x 2k7 Ω resistor • Variable DC power supply • 3 x 2k2 Ω variable POTs • Wire-stripper • 1 x LM 741 IC • Side cutters • Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 24 DBE/PAT 2019 NSC 4.3.7 PROCEDURE (a) Construct the circuit as in FIGURE 3.2 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 2 3 5 (5) FIGURE 3.2 (b) Use the 2k2 Ω POTs to set V1, V2 and V3 to the voltages as indicated in the table below. Measure the output values and populate the table below. (c) V1 + V2 + V3 = Vout 3 + 2,5 + 1,75 = 1,5 + -4 + 2,2 = 5 + -4,5 + 1 = -4 + 1,5 + 2,5 = -1,5 + -2,25 + -3,25 = (5) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 25 DBE/PAT 2019 NSC 4.3.8 CONCLUSION (5) 4.3.9 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 4 (4) Subtotal: Activity 3B [19] Subtotal: Activity 3A (21) Subtotal: Activity 3B (19) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 26 DBE/PAT 2019 NSC 4.4 Simulation 4: Connect a 7-segment display to a 4-bit BCD 7-segment display driver Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.4.1 PURPOSE Construct a simple circuit to connect a 7-segment display to a 4-bit BCD 7-segment display driver. ACTIVITY 4 A: Connect a 7-segment display to a 4-bit BCD 7-segment display driver 4.4.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 4 x LEDs • Breadboard • 4 x 390 Ω resistors • Variable DC power supply • 7 x 1k resistors • Wire-stripper • CD4511 IC • Side cutters • CD4518B IC • 5 x SPST switches • 7-segment display 4.4.3 PROCEDURE (a) Construct the circuit as below. NOTE: An alternative circuit can be used. b c 7-SEGMENT a g d DISPLAY f e 1K each resistor 13 12 11 10 9 15 14 a b c d e f g SW3 CD4511 SW4 D C B A 6 2 1 7 6 5 4 3 Q4A Q3A Q2A Q1A D1 D2 D3 D4 CD4518B CKA ENA CKA Res etA R1 R2 R3 R4 GND1 GND2 GND3 GND4 CLK SW1 SW2 GND Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 27 DBE/PAT 2019 NSC FACET SHEET 8A: Connect a 7-segment display to a 4-bit BCD 7-segment display driver FACETS FACET 1 FACET 2 FACET 3 FACET 4 MAXIMUM LEARNER'S POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/ Collect instruments – Collect hand tools (1) simulation correctly (1) mini-trainer (1) oscilloscope (1) 4 Hand tools Use side cutters Use wire-stripper 2/2 = 1 correctly (1) correctly (1) Preparation for insertion Check the datasheet on Set supply voltage of components into the ICs (1) correctly at +9 V (1) 2 breadboard Correct connection on 8 nodes for correct 20 nodes for correct breadboard – nodes and connection of connection of CD4511 IC polarity CD4518B IC (8/2 = 4) and the 7-segment 14 display (20/2 = 10) Housekeeping Cleaning the working area Placing tools back to the 2 after the experiment (1) places after work (1) Safety Observing safety before Observing safety after 2 being reminded (2) being reminded (1) TOTAL 25 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 28 DBE/PAT 2019 NSC ACTIVITY 4B: Conduct the following steps and answer the questions in the spaces provided. IC CD4185 GIVEN CODE 7-SEGMENT DISPLAY (a) Which number is displayed on the 7-segment display if the binary number 0111 is illuminated on the output LEDs of the counter? (3) (b) Which number is displayed on the 7-segment display if the binary number 1000 is illuminated on the output LEDs of the counter? (3) (c) Which number is displayed on the 7-segment display if the binary number 1001 is illuminated on the output LEDs of the counter? (3) (d) Which number is displayed on the 7-segment display if the binary number 0011 is illuminated on the output LEDs of the counter? (3) (e) Which number is displayed on the 7-segment display if the binary number 0101 is illuminated on the output LEDs of the counter? (3) Subtotal: Activity 4B [15] Subtotal: Activity 4A (25) Subtotal: Activity 4B (15) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 29 DBE/PAT 2019 NSC 5. SECTION B – DESIGN AND MAKE Design and Make Project INSTRUCTIONS •Time: January to August This section is COMPULSORY for all 2019 learners. • The teacher will choose a circuit for the project. •Learner Name: constructed must include at least (but is not limited to): Any project o Seven components School: o A variety of components (both active and passive) o PCB making in some form Class: o Soldering o An enclosure with a switch and protection •Title/Type of Project: The checklist must be used to ensure that all _____ the required tasks for the PAT have been completed. INSTRUCTIONS • This section is COMPULSORY for all learners. • The teacher will choose a circuit for the project. • Any project constructed must include at least (but is not limited to): o Seven components o A variety of components (both active and passive) o PCB making in some form o Soldering o An enclosure with a switch and protection • The checklist below must be used to ensure that all the required tasks for the PAT have been completed. PAT CHECKLIST NO. DESCRIPTION TICK () NO YES Design and Make: Part 1 1. Circuit diagram drawn   2. Circuit description filled in   3. Component list completed   4. Tools list for circuitry populated   5. Measuring instrument list filled in   6. Evidence of prototyping printed and pasted into the file   7. Learner's own Veroboard/PCB planning/design printed and included in file   Design and Make: Part 2 1. Enclosure design completed and included in the file   2. Unique name written down and on the enclosure   3. Logo designed and on the enclosure   Miscellaneous 1. Enclosure included in the project   2. Enclosure prepared and drilled according to the design   3. Enclosure finished off and completed with name and logo   4. PCB securely mounted in the enclosure using acceptable techniques   5. Circuit inside the enclosure accessible   6. Internal wiring neat and ready for inspection   7. File and project completed and ready for moderation at the workshop/room   Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 30 DBE/PAT 2019 NSC 5.1 Design and Make: Part 1 5.1.1 Circuit diagram Draw a circuit diagram of your project. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 31 DBE/PAT 2019 NSC 5.1.2 Project: Description of operation Use the space below to provide an overview of how the project functions. Use your own words and do some research of your own. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 32 DBE/PAT 2019 NSC 5.1.3 Component list Draw up a list of components you will need from the circuit diagram. LABEL DESCRIPTION AND VALUE QUANTITY 5.1.4 Tools/Instrument list Draw up a list of tools you will need to complete the PAT circuitry. You may add to the list as you proceed through the PAT. DESCRIPTION PURPOSE/USE 5.1.5 Evidence of prototyping Take photographs of the working prototype on the breadboard using a digital camera or cellphone and insert here. Add your name on the photograph. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 33 DBE/PAT 2019 NSC 5.1.6 Veroboard planning/PCB design Design a Veroboard OR PCB design for the circuit you are going to build. ONLY do one or the other; do NOT do both. Place your design below. Final Design – Veroboard Same size and placement of components Use an X to show breaks made on the track. Printed circuit-board planning Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 34 DBE/PAT 2019 NSC 5.2 Assessment of the Design and Make Phase: Part 1 Achieved  Mark NO. FACET DESCRIPTION Not achieved  Circuit Diagram 1. The circuit diagram was drawn using EGD equipment. 1 2. The circuit diagram was drawn using EGD equipment and 1 CAD/any electronic design software. 3. The circuit diagram was drawn using correct symbols. 1 4. The circuit diagram has all labels – R1, C1, Tr1, etc. 1 5. The circuit diagram has all component values –100 Ω, 1 220 μF, etc. 6. The circuit diagram has a name. 1 7. The circuit diagram has a frame and title block (EGD 1 approach). Component List 8. Labels correlate with circuit diagram. 1 9. Description and values correlate with circuit diagram. 1 10. Quantities are correct. 1 Description of Operation 11. Basic function of the circuit is described correctly. 1 12. All subcircuits in the circuit diagram and component list are 1 included in the description. 13. Purposes of subcircuits in the circuit diagram are described 1 correctly. 14. Learner used own interpretation and did not copy from 1 another source verbatim. 15. Sources are acknowledged. 1 Tools/Instrument List 16. The tools/instrument list has been completed. 1 17. The tools/instruments listed all have a purpose for being used. 1 Evidence of Prototyping on Breadboard 18. Unique, original photos of the prototyping are included. 1 19. Unique, original photos include the learner name. 1 20. Photos are clear and in focus: 1 All components are clearly identifiable. 21. Prototype is operational. No photo, no mark. 2 22. Video of working prototype is available as confirmation. 3 PCB Design 23. Board design is included in the PAT file. 1 24. Component overlay showing placement is included. 1 25. Components are labelled the same as in the circuit diagram. 1 26. The design is original and does not match any other learner's 1 design. 27. Board layout (tracks/current flow) is functional and matches 1 the original circuit diagram. Circuit Board Manufacturing 28. Circuit board is etched neatly according to the PCB design. 5 29. The PCB is tinned neatly. 1 30. The soldered PCB, solder side, is covered with a clear 1 protective coating (Plastik 70/clear lacquer). 31. Holes are drilled neatly and are aligned in the middle of the 1 pads on the PCB. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 35 DBE/PAT 2019 NSC 32. Mounting holes of the PCB are drilled symmetrically. 1 33. All burrs are removed. 1 34. The PCB is cut neatly/squarely and edges are filed neatly. 1 35. Axial and radial components are placed neatly and flush with 1 the board. 36. Component orientation are aligned between similar 1 components (e.g. the gold band of all resistors are placed on the same side). 37. Soldered components – leads are cut off, flush and neat on 2 the solder side. 38. More than 60% of the solder joints are shiny (not dry joints). 2 39. Wire insulation is stripped to the correct length (no extra 2 copper showing). 40. Wiring is long enough to allow for dismantling and inspection. 1 41. Wiring is wrapped neatly. 1 42. A power switch is included and fitted to the enclosure. 2 43. A fuse/protection is included and fitted correctly where 2 applicable. 44. Wiring entering/exiting the enclosure is provided with a 2 grommet/applicable fittings/sockets where applicable. 45. Batteries are mounted using a battery housing/mounting 1 bracket and battery clip (NO double-sided tape). 46. The project has a pilot light/LED installed in the enclosure 2 showing when the circuit is operational. (Switch is on – must go out when fuse is blown.) 47. The project is fully operational and commissioned/installed in 10 the enclosure. TOTAL (PART 1 = 70 marks) NOTE: In projects where facets 43 and 44 are not applicable, the projects should be marked out of 66 and the marks adjusted accordingly. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 36 DBE/PAT 2019 NSC 5.3 Design and Make: Part 2 (a) Enclosure design • Design an enclosure for your project. • NO FREEHAND DRAWINGS. • Draw using EGD equipment OR use a CAD program. • Draw in first-angle orthographic projection. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 37 DBE/PAT 2019 NSC (b) Manufacture the enclosure neatly according to your design. (c) Choose a name for your device. Write down the name of the device below. (d) Design a unique logo for your device below. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 38 DBE/PAT 2019 NSC 5.4 Assessment of the Design and Make Phase: Part 2 Achieved  Mark Not achieved  NO. FACET DESCRIPTION Enclosure Design 1. Enclosure design is included in first-angle orthographic 1 projection. 2. Drawn design includes a title box and page border. 1 3. Isometric drawing included additionally. 1 4. Dimensions are included. 1 5. The name of the device is written in the PAT document. 1 6. The logo design is in the PAT document. 1 Subtotal (6 marks max.) Enclosure Manufacturing 7. Enclosure matches the design. 1 – Dimensions and placement correlate. 8. Name of the device is on the enclosure. 1 9. The logo design is on the enclosure. 1 10. The logo design on the enclosure is durable and not 1 merely a paper pasted on the enclosure (painted/used decoupage/screen printed/sublimation printed). 11. The enclosure is manufactured from scratch. 3 Does NOT include: cardboard, paper, margarine container Does include: sheet metal, Perspex, Plexiglas, wood, glass and other raw materials, injection-moulded plastic boxes 12. Holes/Cut-outs in the enclosure are made with the 2 appropriate tools. 13. Specification plate with the learner's name, operating 1 voltage, fuse rating and additional information on the project. 14. Enclosure is neatly prepped, painted and aesthetically 2 pleasing. 15. The circuit board is mounted using appropriate methods 1 inside the enclosure. (NO double-sided tape, Prestik, glue, chewing gum, masking tape, etc.) Subtotal (14 marks max.) TOTAL (PART 2 = 20 marks) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 39 DBE/PAT 2019 NSC 6. PROJECTS 6.1 Practical Project 1: Traffic light RESOURCES TOOLS/INSTRUMENTS MATERIALS • Oscilloscope (analogue/digital) • 100 kΩ resistor • Analogue/Digital trainer with dual power supply • 220 Ω resistor x 3 • Electronics multimeter • 22 kΩ resistor x 1 • Soldering iron • LED green x 1 • Helping hands • LED yellow x 1 • PCB etching tank or similar • LED red x 1 • Solder sucker • 1 µF capacitor x 2 • Wire-stripper • 10 µF capacitor x 1 • Side cutters • 470 kΩ variable resistor x 1 • IC NE555 • IC CD 4017 • 1N4007 diode x 6 • PCB 150 x 100 mm • Solder • PCB etching chemicals CIRCUIT DIAGRAM TRAFFIC LIGHT CIRCUIT 1mF 100K 1mF 8 4 16 7 470K NE 555 3 14 CD 4017 15 22K 6 2 1 5 6 9 11 10 1 2 3 4 7 10mF 220Ω 220Ω 220Ω GREEN YELLOW RED Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 40 DBE/PAT 2019 NSC 6.2 Practical Project 2: Cellphone detector Cellphones are widely used in the world. While people have to be connected to one another, there are situations or places where the usage has to be prohibited, either due to security reasons or because it may be a health hazard. Cellphone detection has been under investigation for a long time. There are techniques that have been formulated or proposed on how to detect cellphones. Most of them use features such as the audio system, RF system and common materials of the cellphone to try and look into how it can be used to detect mobile phones. This project utilises the RF system of the cellphone as the feature to detect its presence. A circuit that detects signals of the range 0,9 GHz to 3 GHz is used to detect a cellphone when in use. When the signal is detected, an LED blinks to indicate the usage of a cellphone within a radius of 1,5 metres. It is therefore a reality that mobile usage in some places must be prohibited. Due to the privacy laws that limit the use of cellphone jammers, cellphone detectors must be designed and installed so that in case a person gets into such places with a cellphone, they can be notified and either be told to switch it off or to remove it. The effectiveness of cellphone detectors is that they continually scan for the presence and usage of cellphones and sound an alarm to notify the user or security personnel. This project is limited to the detection of a cellphone that is in use: on call, communication via SMS and internet access. The detection of cellphones that are on standby mode, switched off or on airplane mode will not be included in this project. TOOLS/INSTRUMENTS MATERIALS • Oscilloscope (analogue/digital) • Op amp CA3130 • Analogue/Digital trainer with dual power supply • 2,2 M resistor (2) • Electronics multimeter • 100 K resistor (1) • Soldering iron • 1 K resistor (3) • Helping hands • 100 nF capacitor (4) • PCB etching tank or similar • 22 pF capacitor (2) • Solder sucker • 100 uF capacitor • Wire-stripper • Breadboard • Side cutters • 9 volt battery • Battery connector • LED • Transistor BC547 • Transistor BC557 • Connecting wires • Buzzer • Antenna Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 41 DBE/PAT 2019 NSC Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 42 DBE/PAT 2019 NSC 7. CONCLUSION Upon completion of the practical assessment task learners should be able to demonstrate their understanding of the industry, enhance their knowledge, skills, values and reasoning abilities, as well as establish connections to life outside the classroom and address real-world challenges. Furthermore, the PAT develops learners' life skills and provides opportunities for learners to engage in their own learning. Copyright reserved