Electrical Technology PAT GR 12 2019 (Electronics) Eng

Downloaded from hlayiso.com ELECTRICAL TECHNOLOGY – ELECTRONICS GUIDELINES FOR PRACTICAL ASSESSMENT TASKS GRADE 12 2019 These guidelines consist of 61 pages. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 2 DBE/PAT 2019 NSC TABLE OF CONTENTS 1. INTRODUCTION .................................................................................................................3 2. TEACHER GUIDELINES ........................................................................................................5 2.1 How to administer PATs ........................................................................................................5 2.2 How to mark/assess the PATs ...............................................................................................5 2.3 PAT assessment management plan........................................................................................5 2.4 Moderation of PATs ..............................................................................................................6 2.5 Absence/Non-submission of tasks .........................................................................................7 2.6 Simulations ...........................................................................................................................7 2.7 Projects ................................................................................................................................8 2.8 Working marks sheet ............................................................................................................9 3. LEARNER GUIDELINES ...................................................................................................... 10 3.1 Instructions to the learner ................................................................................................... 11 3.2 Declaration of authenticity (COMPULSORY) ......................................................................... 11 4. SIMULATIONS .................................................................................................................. 12 4.1 Simulation 1: RLC circuit ...................................................................................................... 12 4.2 Simulation 2: The field-effect transistor ............................................................................... 17 4.3 Simulation 3: Amplifiers using a JFET and a Darlington pair .................................................. 23 4.4 Simulation 4: JFET as an amplifier ....................................................................................... 29 4.5 Simulation 5: Colpitts oscillator ........................................................................................... 32 4.6 Simulation 6: 741 bi-stable multivibrator ............................................................................. 36 4.7 Simulation 7: 741 op amp and 555 IC ................................................................................... 39 4.8 Simulation 8: 741 op amp Schmidt trigger and summing amplifier circuit ............................. 44 5. SECTION B – DESIGN AND MAKE ...................................................................................... 48 5.1 Design and Make: Part 1 ..................................................................................................... 49 5.2 Assessment of the Design and Make Phase: Part 1 ............................................................... 53 5.3 Design and Make: Part 2 ..................................................................................................... 55 5.4 Assessment of the Design and Make Phase: Part 2 .............................................................. 57 6. PROJECTS ........................................................................................................................ 58 6.1 Practical Project 1: 5 Watt mini-amplifier (portable speaker)................................................ 58 6.2 Practical Project 2: Traffic light ........................................................................................... 60 7. CONCLUSION ................................................................................................................... 61 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 3 DBE/PAT 2019 NSC 1. INTRODUCTION The 17 Curriculum and Assessment Policy Statements subjects which contain a practical component all include a practical assessment task (PAT). These subjects are: • AGRICULTURE: Agricultural Management Practices, Agricultural Technology • ARTS: Dance Studies, Design, Dramatic Arts, Music, Visual Arts • SCIENCES: Computer Applications Technology, Information Technology, Technical Sciences • SERVICES: Consumer Studies, Hospitality Studies, Tourism • TECHNOLOGY: Civil Technology, Electrical Technology, Mechanical Technology and Engineering Graphics and Design A practical assessment task (PAT) mark is a compulsory component of the final promotion mark for all candidates offering subjects that have a practical component and counts 25% (100 marks) of the end-of-the-year examination mark. The PAT is implemented across the first three terms of the school year. This is broken down into different phases or a series of smaller activities that make up the PAT. The PAT allows for learners to be assessed on a regular basis during the school year and it also allows for the assessment of skills that cannot be assessed in a written format, e.g. test or examination. It is therefore important that schools ensure that all learners complete the practical assessment tasks within the stipulated period to ensure that learners are resulted at the end of the school year. The planning and execution of the PAT differs from subject to subject. Practical assessment tasks are designed to develop and demonstrate a learner's ability to integrate a variety of skills in order to solve a problem. The PAT also makes use of a technological process to inform the learner what steps needs to be followed to derive a solution for the problem. The PAT consists of four or more simulations and a practical project. The teacher may choose any one of the practical projects and any four simulations available for power systems. The teacher must apply assessment on an ongoing basis at the same time that the learner is developing the required skills. Four simulations should be completed by the learners, in addition to the manufacturing of a practical project. The PAT incorporates all the skills the learner has developed throughout the year. The PAT ensures that all the different skills will be acquired by learners on completion of practical work, as well as the correct use of tools and instruments. Requirements for presentation A learner must present the following: • PAT file with all the evidence of simulations, design and prototyping. A copy of the PAT 2019 cover page. The relevant simulations and assessment sheets should be copied and handed to each learner to include in the file. • Practical project with: o Enclosure:  The file must include a design.  The enclosure and the design must match.  No cardboard boxes are allowed. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 4 DBE/PAT 2019 NSC  Plastic and metal enclosures are acceptable.  The enclosure should be accessible for scrutiny inside.  Lids that are secured with screws are preferred. o Circuit board:  The file should include the PCB design.  The PCB must be mounted inside the enclosure in such a manner that it can be removed for scrutiny.  Switches, potentiometers, connectors and other items must be mounted.  Wiring must be neat and bound/wrapped.  Wiring must be long enough to allow for the PCB to be removed and inspected with ease. o Logo and name:  The file should contain the logo and name design.  Logo and name must be prominent on the enclosure. The PAT will have a financial impact on the school's budget and school management teams are required to make provision to accommodate this particular expense. PAT components and other items must be acquired timeously, for use by the learners, before the end of the first term at the start of the academic year. It is the responsibility of the HOD to ensure that the teacher is progressing with the PAT from the start of the school year. Provincial departments are responsible for setting up moderation timetables and consequently PATs should be completed in time for moderation. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 5 DBE/PAT 2019 NSC 2. TEACHER GUIDELINES 2.1 How to administer PATs Teachers must ensure that learners complete the simulations required for each term. The project should be started in January in order to ensure its completion by August. In instances where formal assessments take place, the teacher has to assume the responsibility thereof. The PAT should be completed during the first three terms and must be ready at the start of PAT moderation. Teachers must make copies of the relevant simulations and hand it to learners at the beginning of each term. The PAT must not be allowed to leave the workshop and must be kept in a safe place at all times when learners are not working on it. The weightings of the PAT must be adhered to and teachers are not allowed to change weightings for the different sections. 2.2 How to mark/assess the PATs The PAT for Grade 12 will be set and assessed internally, but moderated externally. All formal assessment will be done by the teacher. The teacher is required to produce a working model and model answer file that sets the baseline for assessment at a Highly Competent Level for every project choice exercised by the learners. This file must include all the simulations with answers the teacher has done him/herself. The teacher will use the model answers and project to assess the simulations and projects of the learners. Once a facet sheet has been completed by the teacher, assessment will be deemed to be complete. No re-assessment will be done once the facet sheets have been completed and captured by the teacher. Learners must ensure that the work is done to the required standard before the teacher finally assesses the PAT during each stage of completion. 2.3 PAT assessment management plan The assessment plan for the PAT is as follows: TIME FRAME ACTIVITY RESPONSIBILITY Preparation for Teacher – Builds the models and works out the model answers PAT 2019 for the simulations for 2019. Identifies shortages in tools, equipment and consumable items for simulations that must be procured in 2019 SMT – Receives procurement requests from teachers and processes payments for the acquisition of required items January – Simulations 1 Teacher – Copies and hands out simulations March 2019 and 2 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday January 2019 PAT project – Teacher – Obtains quotations for PAT projects procurement Principal – Approves PAT procurement for PAT projects Teacher – Ensures that PAT projects are ordered and delivered HOD – Checks in on teacher to see if the process is adhered to Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 6 DBE/PAT 2019 NSC February 2019 PAT project – Teacher – Ensures that there is secure storage for PAT projects learners Teacher – Hands out and takes in PAT projects commence Teacher – Includes practical sessions for learners to complete with project the PAT project every week Learners – Commence with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis April – Moderation of District subject facilitator/subject specialist will visit the school June 2019 Simulations 1 and moderate Simulation 1 and 2 and 2 10% of learners' work is moderated April – Simulations 3 Teacher – Copies and hands out simulations June 2019 and 4 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday April – PAT project – Teacher – Ensures that there is secure storage for PAT projects June 2019 learners Teacher – Hands out and takes in PAT projects continue with Teacher – Includes practical sessions for learners to complete project the PAT project every week Learners – Continue with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis July holidays PAT Learners that are behind on the PAT are required to complete 2019 intervention the project during this holiday. July – Moderation of District subject facilitator/subject specialist will visit the school August 2019 Simulations 3 and moderate Simulations 3 and 4 – different learners from the and 4 previous term 10% of learners' work is moderated July – PAT project – Teacher – Ensures that there is secure storage for PAT projects August 2019 completion Teacher – Hands out and takes in PAT projects Teacher – Completes the PAT project with learners and compiles the PAT file Learners – Completes the PAT project and file HOD – Checks to see that 100% of the PAT files and projects are completed and assessed September – PAT PAT projects are moderated by subject facilitators/subject October 2019 moderation specialists from the province and learners are available to demonstrate skills 10% of learners are moderated randomly 2.4 Moderation of PATs Provincial moderation of each term's simulations will start as early as the following term. Simulations 1 and 2 should be moderated as soon as the second term starts. Similarly, Simulations 3 and 4 will be moderated in July. The project will, however, only be moderated on completion. During moderation of the PAT the learner's file and project must be presented to the moderator. The moderation process is as follows: • During moderation, learners are randomly selected to demonstrate the different simulations. All four simulations will be moderated. • The teacher is required to build an exemplar model for each project type chosen for the school. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 7 DBE/PAT 2019 NSC • This model must be on display during moderation. • The teacher's model forms the standard of the moderation at Level 4 (Highly Competent). • Level 5 assessments must exceed the model of the teacher in skill and finishing. • Learners who are moderated will have access to their files during moderation and may refer to the simulations they completed earlier in the year. • Learners may NOT ask assistance from other learners during moderation. • All projects and files must be on display for the moderator. • If a learner is unable to repeat the simulation or cannot produce a working circuit during moderation, marks will be deducted and circuits assessed as not being operational. • The moderator will randomly select no fewer than two projects (not simulations) and the learners involved will have to explain how the project was manufactured. • Where required, the moderator should be able to call on the learner to explain the function and principles of operation, and request the learner to exhibit the skills acquired through the simulations for moderation purposes. • On completion the moderator will, if needed, adjust the marks of the group upwards or downwards, depending on the outcome of moderation. • Normal examination protocols for appeals will be adhered to, if a dispute arises from adjustments made. 2.5 Absence/Non-submission of tasks The absence of a PAT mark in Electrical Technology without a valid reason: The learner will be given three weeks before the commencement of the final end-of-year examination to submit outstanding task. Should the learner fail to fulfil the outstanding PAT requirement, such a learner will be awarded a zero (0) for that PAT component. 2.6 Simulations Simulations are circuits, experiments and tests/tasks which the learner will have to build, test and measure and practically do as part of the development of practical skills. These skills have to be illustrated to the external moderator that visits the school at intervals during the school year. Teachers who make use of simulation programs on a computer may use it for the learners to practice on. However, it is required that the circuit be built using real components and that measurements be made with actual instruments for the purposes of assessment and moderation. The correct procedure for completing simulations is outlined below for teachers and school management teams who are responsible for the implementation of the PAT in Electrical Technology. STEP 1: The teacher will choose simulations from the provided examples. STEP 2: Compile a list of the components needed for every simulation. Add extra components as these items are very small and you will need extras, as these items get lost/damaged very easily when learners are working with it. STEP 3: Contact three different electronics component suppliers for comparative quotations. STEP 4: Submit the quotations to the SMT for approval and procurement of the items. STEP 5: Place the components in storage. Collate items for each simulation, thus making it easier to distribute and use during practical sessions. Ensure that different values of components do not mix, as this would lead to components being used incorrectly and this could damage the component and in extreme cases, the equipment used. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 8 DBE/PAT 2019 NSC STEP 6: Copy the relevant simulations and hand them out to learners at the start of the term. Teachers are allowed to adjust circuits and component values to suit their environment/ resource availability. Teachers are required to develop a set of model answers in the teacher's file. Moderators will use the teacher's model answers and artefacts when moderating. 2.7 Projects The projects are construction projects teachers can choose for their learners. These projects are based on proven circuits provided from schools and subject advisors. The projects are based on working prototypes and require careful construction in order for it to operate correctly. Projects are varied in cost and teachers must ensure that the projects chosen fall within the scope of the school's budget. Once the teacher has decided on a circuit, he/she must construct the prototype. Thereafter, copies of the provided circuit can be made and distributed to learners. They MUST redraw these circuits in their file correctly. The description of the operation of the circuits is NOT complete. It is required of learners to interrogate the function of the components in the provided circuit. They should elaborate on the purpose of components in the circuit. It is recommended that those learners investigate similar circuits available on the internet and in the school library or workshop reference books. Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 9 DBE/PAT 2019 NSC 2.8 Working marks sheet (A working Excel file is provided with this PAT.) PAT mark sheet Term 1 Term 2 Project Mark out of 100 Moderated Mark Total = Design Design Term 1 + Simulation Simulation Simulation Simulation and and Term 2 + 1 2 3 4 Make Make Project Part 1 Part 2 No. Name of Learner 40 40 40 40 70 20 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Total Average Teacher Name: Principal Name: Moderator Name: Signature: Signature: Signature: School Stamp Date: Date:_________________________ Date:__________________________ Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 10 DBE/PAT 2019 NSC 3. LEARNER GUIDELINES PAT 2019 cover page (Place this page at the front of the PAT.) Department of Basic Education Grade 12 CAPS for Technical High Schools Practical Assessment Task – Electrical Technology Time allowed: Terms 1–3 (2019) Learner Name: Class: School: Specialisation: ELECTRONICS Complete any FOUR simulations. Project (Write the name of the project): _____________________________ Evidence of moderation: NOTE: When the learner evidence (LE) selected has been moderated at school level, the table will contain evidence of moderation. Provincial moderators will sign the provincial moderation and only sign if re-moderation is needed. Moderation Signature Date Signature Date School-based Provincial moderation Re-moderation Mark allocation Moderated PAT Component Maximum Mark Learner Mark Mark Simulation 1 40 Simulation 2 40 Simulation 3 40 Simulation 4 40 Design and Make Project – Circuit 70 Design and Make Project – Enclosure 20 Total 250 Copyright reserved

Downloaded from hlayiso.com Electrical Technology 11 DBE/PAT 2019 NSC 3.1 Instructions to the learner • The PAT counts 25% of your final promotion mark. • All work produced by you must be your own effort. Group work and co-operative work are not allowed. • The PAT must be completed over three quarters. • The PAT file must contain four simulations and a practical project. • Calculations should be clear and include units. Calculations should be rounded off to TWO digits. SI units should be used. • Circuit diagrams can be hand-drawn or drawn on CAD. NO photocopies or scanned files are allowed. • Photos are allowed and can be in colour or greyscale. Scanned photos and photocopies are allowed. • Learners with identical photos will be penalised and receive zero (0) for that section. • This document must be placed inside your PAT file together with the other evidence. 3.2 Declaration of authenticity (COMPULSORY) Declaration: I _____ (Name) herewith declare that the work represented in this file is entirely my own effort. I understand that if proven otherwise, my final results may be withheld. _____ Signature of learner _____ Date Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 12 DBE/PAT 2019 NSC 4. SIMULATIONS 4.1 Simulation 1: RLC circuit Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.1.1 AIM • To build a resonance RLC-series circuit • To determine the resonant frequency by measuring the reactive voltages • To measure the total current of a series RLC-circuit over a wide range of frequencies • To build a resonance RLC-parallel circuit • To measure the current through the inductor and capacitor of a parallel RLC circuit over a wide range of frequencies • To compare the readings in a series RLC circuit to a parallel RLC circuit 4.1.2 COMPONENT LIST • Audio transformer (Interstage impedance matching transformer found in modems and audio circuits. The value is not critical.) • 0,1 uF capacitor (104) • 1 K (Brown Black Red 5% – ¼ Watt) • Signal generator (Disconnect the earth terminal of the FG.) • Experiment board • Connecting wires • 4 x multimeters • Oscilloscope with two probes (Disconnect the earth terminal of the oscilloscope.) 4.1.3 RLC SERIES CIRCUIT (a) Before connecting the circuit, measure the following accurately: Exact resistance of R (will differ slightly from learner to learner): R=__________ Exact resistance of L (the resistance of the coil being used): RL=__________ (2) (b) Build the given circuit diagram on your experiment board. You will be assessed using the rubric on the next page. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 13 DBE/PAT 2019 NSC LEVEL DESCRIPTOR MARKS OBTAINED 0 1 2 4 The candidate The candidate The candidate The candidate was not able to was able to was able to constructed the construct the partially construct correctly construct circuit correctly circuit on his own. the circuit on his the circuit with the without the own. assistance of the assistance of the teacher. teacher. The candidate The cadidate was The candidate The candidate was not able to able to partially connected the connected the connect the connect the measuring measuring measuring measuring instruments instruments instruments. instruments to the correctly and correctly and circuit. measured the measured the voltages and voltages and currents after the currents on his assistance of the own. teacher. (8) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 14 DBE/PAT 2019 NSC 4.1.4 PROCEDURE (a) Set the function generator to a sine wave and adjust the voltage to between 3–8 V sine wave. (Set the voltage as high as the frequency generator allows.) Set the frequency to 1 kHz. (Teachers are requested to change the frequency for each learner. Use between 150–500 Hz so that each learner has a unique frequency). Once the voltage is set, do not change the amplitude of the voltage. (b) Connect the multimeters to reflect the following voltages: - VL (across the inductor) - VC (across the capacitor) - VR (across the resistor) - VT (total voltage) (Meters must be true RMS meters set to AC to ensure correct readings.) (c) Calculate the total current in the circuit using VR and the measured value of R. (3) (d) Show on the oscilloscope the phase relationship between VT and VL. (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 15 DBE/PAT 2019 NSC (e) Show on the oscilloscope the phase relationship between VT and VC. (4) (f) Calculate the impedance of the circuit. (3) (g) Calculate Xc using the specific frequency assigned to you. (3) (h) Calculate X using the following: (2) (i) Calculate XL from X and XC. (3) (j) Now calculate L from XL. (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 16 DBE/PAT 2019 NSC (k) Tabulate your values in the following table and compare with given results: Learner Results V Coil VC VT IT RL Z X XL XC L Typical Values V Coil VC VT IT RL Z X XL XC L 6,6 V 4,5 V 7,9 V 3,1 mA 1 000 Ω 2 548 Ω - 740 Ω 1 592 Ω 117 mH (l) Are the learner values exactly the same as the typical values? Draw a conclusion and motivate your answer. (3) (m) Read the conclusion below. Explain how the voltages in a RLC series circuit can be leading and lagging. Why is reference made to the phase shift of the voltages and not current in this instance? (2) CONCLUSION In a series AC circuit the current is equal in all components. The voltage in the inductor leads the supply voltage and the voltage in the capacitor lags the supply voltage. TOTAL: 40 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 17 DBE/PAT 2019 NSC 4.2 Simulation 2: The field-effect transistor Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.2.1 PURPOSE Construct simple circuits using JFET and MOSFET, and display the input/output wave forms on an oscilloscope. ACTIVITY 2A: Construct a circuit using a JFET as a switch. 4.2.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS CONSUMABLES • Analogue/Digital trainer • 1 x 6 V buzzer • 2 x multimeters • 1 x J176 JFET P-channel (Any suitable • Variable DC power supply JFET may be used.) • Wire-stripper • Connecting wires • Side cutters 4.2.3 PROCEDURE (a) Connect the circuit on the breadboard as shown in FIGURE 2.1. FIGURE 2.1: JFET switch (b) Close the switch and observe the output of the buzzer. Record your observation. (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 18 DBE/PAT 2019 NSC (c) Open the switch and observe the output of the buzzer. Record your observation. (2) (d) CONCLUSION Explain what can be deduced from your observation with regard to a JFET as a switch. (2) Subtotal: Activity 2A [6] Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 19 DBE/PAT 2019 NSC FACET SHEET 2A: Construct a circuit using a JFET as a switch. FACETS FACET 1 FACET 2 FACET 3 FACET 4 MAXIMUM LEARNER'S POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/ Collect instruments – Collect hand tools (1) 4/2 = 1 simulation correctly (1) mini-trainer (1) oscilloscope (1) Hand tools Use side cutters Use wire-stripper 2/2 = 1 correctly (1) correctly (1) Preparation for insertion Check the datasheet Set supply voltage Set input voltage 3 of components into on the FET (1) correctly at 6 V (1) correctly at 3–4 V (1) breadboard Correct connection on 6 nodes for correct Polarity of buzzer – Polarity of JFET – 6/2 = 3 breadboard – nodes and connection (6/2 = 3) correct (1) correct (2) polarity Circuit is working Switch = ON Switch = OFF 2 correctly Buzzer is OFF (1) Buzzer is ON (1) Connection of meters Connection of Connection of 2 multimeter across multimeter across input to show 3 V/ output High/Low (1) On/Off (1) Housekeeping Cleaning the working Placing tools back to Disposing of waste 2/2 = 1 area after the the places after work materials correctly experiment (1) (1) after work Safety Observing safety Observing safety after Not observing safety 2/2 = 1 before being reminded being reminded (1) (0) (2) TOTAL 14 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 20 DBE/PAT 2019 NSC ACTIVITY 2B: Construct a circuit using a MOSFET as a switch. 4.2.4 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x 1 KΩ resistor • Analogue/Digital oscilloscope • 1 x MΩ resistor • Function generator • 1 x BS 270 N channel • Variable DC power supply • 1 x LED • Wire-stripper • 1 x toggle switch • Side cutters • Connecting wires 4.2.5 PROCEDURE (a) Connect the circuit as in the given circuit below. FIGURE 2.2: MOSFET (b) Close the switch and observe the output of the LED. Record your findings. (1) (c) Open the switch and observe the output of the LED. Record your findings. (1) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 21 DBE/PAT 2019 NSC (d) Distinguish between a depletion mode MOSFET and an enhancement mode MOSFET. (2) (e) CONCLUSION Explain what can be deduced from your observation with regard to a MOSFET as a switch. (1) Subtotal: Activity 2B [5] Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 22 DBE/PAT 2019 NSC FACET SHEET 2B: Construct a circuit using a MOSFET as a switch. FACETS FACET 1 FACET 2 FACET 3 FACET 4 MAXIMUM LEARNER'S POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/ Collect instruments – Collect hand tools (1) 4/2 = 2 simulation correctly (1) mini-trainer (1) oscilloscope (1) Hand tools Use side cutters Use wire-stripper 2/2 = 1 correctly (1) correctly (1) Preparation for insertion Check the datasheet Set supply voltage Set input voltage 4/2 = 2 of components into on the FET (2) correctly at 6 V (1) correctly at 3–4 V (1) breadboard Correct connection on 6 nodes for correct Polarity of buzzer – Polarity of JFET – 6/2 = 3 breadboard – nodes and connection (6/2 = 3) correct (1) correct (2) polarity Circuit is working Switch = ON Switch = OFF 2 correctly LED is ON (1) LED is OFF (1) Connection of meters Correct setting of Correct connection of Correct reading of the 3 multimeter (1) multimeter in terms of multimeter (1) polarity (1) Housekeeping Cleaning the working Placing tools back to 2/2 = 1 area after the the places after work experiment (1) (1) Safety Observing safety Observing safety after Not observing safety 2/2 = 1 before being reminded being reminded (1) (0) (2) TOTAL 15 Subtotal: Activity 2A (6) Subtotal: Facet Sheet 2A (14) Subtotal: Activity 2B (5) Subtotal: Facet Sheet 2B (15) TOTAL: Simulation 2 [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 23 DBE/PAT 2019 NSC 4.3 Simulation 3: Amplifiers using a JFET and a Darlington pair Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.3.1 PURPOSE Construct a simple amplifying circuit using JFET and a Darlington pair. Display the input/output waveforms on an oscilloscope. ACTIVITY 3A: Using a JFET as an amplifier 4.3.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x 2M2 Ω resistor • Analogue/Digital oscilloscope • 1 x 5k6 Ω resistor • Function generator • 1 x 4k7 Ω pre-set resistor • Variable DC power supply • 1 x 470 Ω resistor • Wire-stripper • 1 x 220 nF capacitor • Side cutters • 1x 10 µF capacitor 32 V • 1 x 22 µF capacitor 32 V • 1 x 2N3819 JFET (2N5459 or 2N5457) • Connecting wires 4.3.3 PROCEDURE (a) Build the circuit diagram on a breadboard. FIGURE 3.1: JFET Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 24 DBE/PAT 2019 NSC (b) Connect the function generator to the input and adjust the voltage to 1 V peak. (c) Connect Channel 1 of the oscilloscope across the input of the amplifier and draw the waveform on the grid provided to scale. (2) (d) Connect Channel 2 of the oscilloscope across the output of the amplifier and draw the waveform on the grid provided to scale. (2) CH1 V/DIV = CH2 V/DIV = T/DIV = CH1 V/DIV = CH2 V/DIV = T/DIV = Channel 1 Channel 2 Compare the two waveforms and draw a conclusion regarding the circuit. (2) Subtotal: Activity 3A [5] Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 25 DBE/PAT 2019 NSC FACET SHEET 3A: Using a JFET as an amplifier FACETS FACET 1 FACET 2 FACET 3 FACET 4 MAXIMUM LEARNER'S POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/ Collect instruments – Collect hand tools (1) 2/2 = 1 simulation correctly (1) mini-trainer (1) oscilloscope (1) Hand tools Use side cutters Use wire-stripper 2/2 = 1 correctly (1) correctly (1) Preparation for insertion Check the datasheet Set supply voltage Set input voltage 3 of components into on the FET (1) correctly at +12 V to correctly at 1 V from breadboard +20 V (1) function generator (1) Correct connection on 6 nodes for correct Polarity of JFET – Polarity of C2 – Polarity of C3 – 6/2 = 3 breadboard – nodes and connection (6/2 = 3) correct (1) correct (1) correct (1) polarity Circuit is working Output amplified (1) Output phase vs input 2 correctly phase (1) Connection of Correct setting of the Correct connection and Correct reading of 6/2 = 3 instruments oscilloscope (2) reading of oscilloscope oscilloscope (2) (2) Housekeeping Cleaning the working Placing tools back to 2/2 = 1 area after the the places after work experiment (1) (1) Safety Observing safety Observing safety after 2/2 = 1 before being reminded being reminded (1) (2) TOTAL 15 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 26 DBE/PAT 2019 NSC ACTIVITY 3B: Using a Darlington transistor as a current amplifier 4.3.4 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 2 x BC 109 NPN transistors • Analogue/Digital oscilloscope • 1 x LED • Function generator • 1 x 470 Ω resistor • Variable DC power supply • 1 x 100 resistor • Wire-stripper • 1 x Darlington transistor (TIP120 or • Side cutters TIP125) • Connecting wires 4.3.5 PROCEDURE (a) Construct the circuit as in the diagram given below. FIGURE 3.2: TRANSISTOR AS A SWITCH (b) Once the switch is closed, observe the brightness of the LED. (c) Replace the single transistor with two identical BC109 transistors as shown below. FIGURE 3.3: TRANSISTOR PAIR (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 27 DBE/PAT 2019 NSC (d) Again, after the switch is closed, observe the brightness of the LED. What can you conclude from your finding? (e) Compare the brightness when one transistor was used and when two transistors were used. (2) (f) Replace the two transistors with a single Darlington transistor (TIP120 or 125) and observe the brightness of the LED. Draw your own conclusion with regard to the observation. (2) Subtotal: Activity 3B [6] Copyright reserved Please turn over

Electrical Technology Downloaded from hlayiso.com 28 DBE/PAT 2019 NSC FACET SHEET 3B: Using a Darlington transistor as a current amplifier FACETS FACET 1 FACET 2 FACET 3 FACET 4 MAXIMUM LEARNER'S POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/ Collect Instruments – Collect hand tools (1) 4/2 = 2 simulation correctly (1) mini-trainer (1) multimeter (1) Hand tools Use side cutters correctly Use wire-stripper 2/2 = 1 (1) correctly (1) Preparation for Check the datasheet on Set supply voltage 2 insertion of the transistor and the correctly at +9 V (1) components into Darlington pair (1) breadboard Correct connection on 6 nodes for correct Polarity of TR1 and Polarity of Darlington Polarity of LED – 8/2 = 4 breadboard – nodes connection (6/2 = 3) TR2 – correct (2) pair – correct (2) correct (1) and polarity Circuit is working When 1 transistor is When 2 transistors are When Darlington pair 3 correctly connected. connected. is connected. Brightness of LED – Brightness of LED – Brightness of LED – normal (1) bright (1) bright (1) Housekeeping Cleaning the working Placing tools back to 2/2 = 1 area after the experiment the places after work (1) (1) Safety Observing safety before Observing safety after 2/2 = 1 being reminded (2) being reminded (1) TOTAL 14 Subtotal: Activity 3A (5) Subtotal: Facet Sheet 3A (15) Subtotal: Activity 3B (6) Subtotal: Facet Sheet 3B (14) TOTAL: Simulation 3 [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 29 DBE/PAT 2019 NSC 4.4 Simulation 4: JFET as an amplifier Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.4.1 PURPOSE The construction of the JFET as amplifier circuit using discrete components and to display the input/output waveforms on the oscilloscope ACTIVITY 4: Construction of the JFET as an amplifier 4.4.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x 2M2 Ω resistor • Analogue/Digital oscilloscope • 1 x 5K6 Ω resistor • Function generator • 1 x 4K7 Ω resistor • Variable DC power supply • 1 x 470 Ω resistor • Wire-stripper • 1 x 220 nF capacitor • Side cutters • 1 x 10 µF capacitor • 1 x 22 µF capacitor • 1 x 2N3819 JFET (2N5459) • Connecting wires V1=12V R3=5.6KΩ C2=220nF C1=220nF 2N3821 Output V2=1Vrms R1=2.2MΩ R=4.7KΩ 100Hz + C3=22ΩF R2=470Ω FIGURE 4.1: CIRCUIT DIAGRAM OF THE JFET AS AN AMPLIFIER Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 30 DBE/PAT 2019 NSC 4.4.3 PROCEDURE Build the circuit diagram on the breadboard as shown in FIGURE 4.1. Connect Channel 1 of the oscilloscope across the input of the amplifier. Draw the INPUT and OUPUT waveforms. Use the values indicated on the grid provided. 4A FACET SHEET: JFET as an amplifier FACETS FACET 1 FACET 2 FACET 3 FACET 4 MARKS MARKS OBTAINED Prepare for the Identified Collect PSU/ Use the Use the simulations components mini-trainer correct correct hand correctly (1) (1) measuring tools (1) (4) instruments (1) Preparation of Circuit Power Function Channels of the diagram built supply generator the components on correctly (1) connected connected oscilloscope (4) the breadboard correctly (1) correctly (1) connected correctly (1) Circuit is Correct Correct Correct Input and working display of the display of the measure- output correctly input output ment of the waveforms (10) waveform (2) waveform (2) gain as volts drawn and time correctly (4) divisions (2) Safety and Observes Observe Cleans the Returns tools housekeeping safety before safety after working area after working reminded (1) being after the (1) (4) reminded (1) experiment (1) 4B INPUT/OUTPUT GRID CH1 V/DIV = CH2 V/DIV = T/DIV = (6) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 31 DBE/PAT 2019 NSC 4C QUESTIONS: 1. Determine the gain of the amplifier. (2) 2. List the components that can be changed to increase or decrease the gain of the amplifier in FIGURE 4.1. (6) 3. Write your conclusion with regard to the measurements of either the voltage or the current you have observed. (4) [40] 4A: Facet Sheet (22) 4B: Input/Output Grid (6) 4C: Questions (12) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 32 DBE/PAT 2019 NSC 4.5 Simulation 5: Colpitts oscillator Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.5.1 PURPOSE Construction of the Colpitts oscillator circuit using discreet components and displaying the input/output waveforms on an oscilloscope 4.5.2 RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer PNP 2N22905 transistor & NPN transistor BC 182 • Analogue/Digital oscilloscope R1= 470 kΩ and R2= 680Ω RC= 2,2KΩ (R1=2KΩ, R2=270KΩ R3=39KΩ, P1=5k Ω) • Function generator C1=0,1µF (C1=47nF) • Multimeter C2=47 nF (C2=0,1µF) • Variable DC power supply C3= 0,1µF (C3= 25µF) • Wire-stripper C4= 47nF (C4= 15nF) • Side cutters C5=0,47 µF • Hook-up leads L=10mH (interstage transformer) Battery= 12 V DC (9 V DC) 4.5.3 PROCEDURE Oscilloscope setting: Channel 1: AC coupled 0,2V/div Channel 2: AC coupled 0,2V/div Time base: 0,2 mS/div – 2: X-Y measurements Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 33 DBE/PAT 2019 NSC ACTIVITY 5: (a) Build the circuit diagram on the breadboard as shown below in FIGURE 5.1. R1=470KΩ RC=2.2KΩ 12V C4=47nF PNP2N22905 C3=0.1 µF C1=0.1 µF R2=680Ω L=10mH C5=0.47µF C2=47nF FIGURE 5.1: COLPITTS OSCILLATOR CIRCUIT (b) Measure and record the following DC voltages: A. VR1 (2) B. VR2 (2) C. VBE (2) D. VCE (2) E. VRC (2) (c) Measure and record the resonance frequency in kHz. (4) (d) Calculate the theoretical resonant frequency. (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 34 DBE/PAT 2019 NSC (e) Replace capacitors C1 with 470 pF and C2 with 1 000 pF respectively. (i) Record the measured frequency of oscillation: Measured frequency: ____________________ kHz (2) (ii) Calculate the theoretical resonant frequency using the new tank circuit values: Calculated frequency: ____________________ ____________________ ____________________ ____________________ ____________________ ____________________ (4) (f) Answer the following questions: (i) State the function of RC. (2) (ii) Explain the function of C1 and C2 based on your findings in (e) (i) and (ii). C1: C2: (4) (g) Refer to FIGURE 5.1 and answer the following questions: (i) Display the output waveform on the oscilloscope when the V/div is set at 2 V and the time/div is set at 500 µs. (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 35 DBE/PAT 2019 NSC (ii) Draw the output waveform. CH1 V/DIV = CH2 V/DIV = T/DIV = (4) (iii) State TWO applications of the circuit in FIGURE 5.1. (2) TOTAL Activity 5: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 36 DBE/PAT 2019 NSC 4.6 Simulation 6: 741 bi-stable multivibrator Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.6.1 AIM • To study the 741 bi-stable multivibrator as a practical circuit • To compare the theory learned in class with the actual circuit • To build a bi-stable multivibrator circuit with the 741 op amp ACTIVITY 6: Construction of a 741 bi-stable multivibrator 4.6.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Experiment board • 741 op amp (DIP8) • Voltmeter • 330 Ω resistor • Dual power supply 9V-0-9V • 1 kΩ resistor • Dual power supply 5V-0-5V • 470 Ω resistor x 2 • Wire-stripper • Red and green LED • Side cutters • Connecting wires 4.6.3 CIRCUIT DIAGRAM Build the given circuit diagram on your experiment board. After you have switched on the circuit, press the set switch. You will be assessed using the rubric below. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 37 DBE/PAT 2019 NSC +5VCC Set +9 VCC 2 - 7 6 741 Reset + 4 330 Ω 470 Ω 3 1 kΩ R1 R2 R4 -5VCC -9 VCC R3 470 Ω D1 D2 D1 = Red D2 = Green FIGURE 6.1: CIRCUIT DIAGRAM OF 741 BI-STABLE MULTIVIBRATOR LEVEL DESCRIPTOR MARKS 1 2 3 5 OBTAINED The learner could The learner The learner The learner not identify the identified the built the circuit managed to correct correct after the identify the components. components but assistance of components could not build the teacher. correctly and the circuit on built the circuit the breadboard. without the assistance of the teacher. The learner could The learner The learner The learner not use the managed to managed to managed to measuring calibrate the use the use the instruments. instruments instruments and instruments and after the managed to get managed to get assistance of ONE reading ALL the the teacher. required after readings the assistance required without of the teacher. the assistance of the teacher. (10) 4.6.4 OBSERVATIONS (a) Press the reset and set switches. Write down your observation. (3) (b) Connect a voltmeter across R3 and measure the reference voltage of the circuit. VReference = (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 38 DBE/PAT 2019 NSC (c) Measure the input voltage to the circuit across R1. NOTE: Do NOT press any switch. VR1= (3) (d) Measure the input voltage across R1 when you press the set switch. VR1= (3) 4.6.5 HOUSEKEEPING When you have obtained all the measurements and the teacher has validated all your answers, you must tidy up your workplace as part of the safety in the workshop. You will be assessed on housekeeping using the rubric below. LEVEL DESCRIPTOR MARK 0 2 3 5 OBTAINED The learner did The learner did The learner did The learner did not do any housekeeping housekeeping, housekeeping housekeeping. after the but only tidied on his/her own teacher up his/her own and helped to reminded the workplace and tidy up the learner. did not help in entire cleaning the workshop. rest of the workshop. TOTAL Activity 6: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 39 DBE/PAT 2019 NSC 4.7 Simulation 7: 741 op amp and 555 IC Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.7.1 PURPOSE Construct a simple circuit using the 741 op amp to build a non-inverting amplifier and display the input/output waveforms on an oscilloscope. ACTIVITY 7A: Constructing a circuit using the 741 op amp 4.7.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x LM741 IC • Analogue/Digital oscilloscope • 1 x 1KΩ resistor • Function generator • 1 x 10 KΩ resistor • Variable DC power supply • Connecting wires • Wire-stripper • Side cutters 4.7.3 PROCEDURE (a) Construct the circuit as in FIGURE 7.1 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 40 DBE/PAT 2019 NSC FIGURE 7.1 (b) Connect the function generator between ground and Vin. (1) (c) Connect Channel 1 to the input and Channel 2 to the output. (d) Set the function generator to give a sine wave output. (e) Adjust the function generator to 1 000 Hz (1 kHz) at a voltage of 1 V peak. (f) Switch on the power to the circuit and observe the input and output waveforms. (g) Draw the input and output waveforms below. INPUT WAVEFORM (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 41 DBE/PAT 2019 NSC OUTPUT WAVEFORM (4) 4.7.4 QUESTIONS (a) Calculate the gain of the amplifier with the given resistor values. (3) (b) State how the gain of the amplifier will be affected if the feedback resistor is halved. (2) 4.7.5 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 3 (3) Subtotal: Activity 7A [21] ACTIVITY 7B: Constructing a circuit using the 555 IC 4.7.6 PURPOSE Construct a simple circuit using the 555 IC to build a clock pulse generator (astable multivibrator) and display the output waveforms on an oscilloscope. 4.7.7 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x 555 timer IC • Analogue/Digital oscilloscope • 1 x 220 Ω resistor • Function generator • 1 x LED • Variable DC power supply • 1 x 10 nF capacitor • Wire-stripper • 1 x 10 KΩ resistor • Side cutters • 1 x 100 KΩ pre-set POT • 1 x 10 µF (electrolytic capacitor 16 V) • Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 42 DBE/PAT 2019 NSC 4.7.8 PROCEDURE (a) Construct the circuit on the breadboard as in FIGURE 7.2 below. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) FIGURE 7.2 (b) Connect Channel 1 of the oscilloscope to the output. (c) Switch the power on to the circuit and observe the output waveform on the oscilloscope and the LED. (d) Draw the output waveform observed on the oscilloscope on the grid below. OUTPUT WAVEFORM (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 43 DBE/PAT 2019 NSC 4.7.9 QUESTIONS (a) List the components responsible for the frequency of the output. (3) (b) Calculate the charging time for the circuit using the given components. (3) 4.7.10 HOUSEKEEPING 1 2 3 The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. The learner failed to get The learner was able to The learner was able to the output wave on the set the oscilloscope and set the oscilloscope and oscilloscope. managed to get the output managed to get the output wave after the assistance wave without the from the teacher. assistance of the teacher. (6) Subtotal: Activity 7B [19] Subtotal: Activity 7A (21) Subtotal: Activity 7B (19) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 44 DBE/PAT 2019 NSC 4.8 Simulation 8: 741 op amp Schmidt trigger and summing amplifier circuit Name of learner: Mark: Class: Date completed: 40 Date assessed: Assessor signature: Date moderated: Moderator signature: 4.8.1 PURPOSE Construct a simple circuit using a 741 op amp to build a Schmidt trigger circuit and a summing amplifier circuit. Display the output waveforms on an oscilloscope. ACTIVITY 8A: Constructing a Schmidt trigger circuit using the 741 op amp 4.8.2 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 1 x LM741 op amp • Analogue/Digital oscilloscope • 2 x 10 KΩ resistors • Function generator • 3 x 1 kΩ resistors • Variable DC power supply • 1 x 2k2 Ω resistor (pre-set POT) • Wire-stripper • 1 x 100 kΩ resistor • Side cutters • 1 x 1MΩ • 1 x LED • Connecting wires 4.8.3 PROCEDURE (a) Construct the circuit as in FIGURE 8.1 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 1 3 4 (4) FIGURE 8.1 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 45 DBE/PAT 2019 NSC (b) Adjust the potentiometer, while observing the output voltage. The output switches to HIGH when Vin is ________V and to LOW when Vin is ________V. The hysteresis is _______V. (3) (c) Replace the 100 k resistor with 10 k. Adjust the input potentiometer slowly. (d) While watching the LED on the output, can you change the output of the comparator to adjust the brightness of the LED? _________. (1) The output now switches to HIGH when the input voltage is ______V and to LOW (1) at ________V. The hysteresis is ________V. (2) (e) Replace the hysteresis resistor with 1 M. The output now switches to HIGH at _________V and to a LOW at _____ V. (2) The hysteresis is ________V. (1) Remove the hysteresis resistor and adjust the potentiometer slowly. 4.8.4 CONCLUSION (3) 4.8.5 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 4 (4) Subtotal: Activity 8A [21] ACTIVITY 8B: Constructing a summing amplifier circuit using the 741 op amp 4.8.6 REQUIRED RESOURCES TOOLS/INSTRUMENTS MATERIALS • Analogue/Digital trainer • 6 x 1k Ω resistors • Analogue/Digital oscilloscope • 4 x 10 kΩ resistors • Function generator • 1 x 2k7 Ω resistor • Variable DC power supply • 3 x 2k2 Ω variable POTs • Wire-stripper • 1 x LM 741 IC • Side cutters • Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 46 DBE/PAT 2019 NSC 4.8.7 PROCEDURE (a) Construct the circuit as in FIGURE 8.2 on the breadboard. The learner was able to The learner was able to The learner was able to construct a minimum part construct a part of the construct the circuit of the circuit correctly circuit correctly without correctly without without assistance. assistance. assistance. 2 3 5 (5) FIGURE 8.2 (b) Use the 2k2 Ω POTs to set V1, V2 and V3 to the voltages as indicated in the table below. Measure the output values and populate the table below. (c) V1 + V2 + V3 = Vout 3 + 2,5 + 1,75 = 1,5 + -4 + 2,2 = 5 + -4,5 + 1 = -4 + 1,5 + 2,5 = -1,5 + -2,25 + -3,25 = (5) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 47 DBE/PAT 2019 NSC 4.8.8 CONCLUSION (5) 4.8.9 HOUSEKEEPING The learner did not do any The learner did The learner did housekeeping duties. housekeeping after being housekeeping without reminded. being reminded. 1 2 4 (4) Subtotal: Activity 8B [19] Subtotal: Activity 8A (21) Subtotal: Activity 8B (19) TOTAL: [40] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 48 DBE/PAT 2019 NSC 5. SECTION B – DESIGN AND MAKE Design and Make Project INSTRUCTIONS •Time: January to August This section is COMPULSORY for all 2019 learners. • The teacher will choose a circuit for the project. •Learner Name: constructed must include at least (but is not limited to): Any project o Seven components School: o A variety of components (both active and passive) o PCB making in some form Class: o Soldering o An enclosure with a switch and protection •Title/Type of Project: The checklist must be used to ensure that all _____ the required tasks for the PAT have been completed. INSTRUCTIONS • This section is COMPULSORY for all learners. • The teacher will choose a circuit for the project. • Any project constructed must include at least (but is not limited to): o Seven components o A variety of components (both active and passive) o PCB making in some form o Soldering o An enclosure with a switch and protection • The checklist below must be used to ensure that all the required tasks for the PAT have been completed. PAT CHECKLIST NO. DESCRIPTION TICK () NO YES Design and Make: Part 1 1. Circuit diagram drawn   2. Circuit description filled in   3. Component list completed   4. Tools list for circuitry populated   5. Measuring instrument list filled in   6. Evidence of prototyping printed and pasted into the file   7. Learner's own Veroboard/PCB planning/design printed and included in file   Design and Make: Part 2 1. Enclosure design completed and included in the file   2. Unique name written down and on the enclosure   3. Logo designed and on the enclosure   Miscellaneous 1. Enclosure included in the project   2. Enclosure prepared and drilled according to the design   3. Enclosure finished off and completed with name and logo   4. PCB securely mounted in the enclosure using acceptable techniques   5. Circuit inside the enclosure accessible   6. Internal wiring neat and ready for inspection   7. File and project completed and ready for moderation at the workshop/room   Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 49 DBE/PAT 2019 NSC 5.1 Design and Make: Part 1 5.1.1 Circuit diagram Draw a circuit diagram of your project. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 50 DBE/PAT 2019 NSC 5.1.2 Project: Description of operation Use the space below to provide an overview of how the project functions. Use your own words and do some research of your own. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 51 DBE/PAT 2019 NSC 5.1.3 Component list Draw up a list of components you will need from the circuit diagram. LABEL DESCRIPTION AND VALUE QUANTITY 5.1.4 Tools/Instrument list Draw up a list of tools you will need to complete the PAT circuitry. You may add to the list as you proceed through the PAT. DESCRIPTION PURPOSE/USE 5.1.5 Evidence of prototyping Take photographs of the working prototype on the breadboard using a digital camera or cellphone and insert here. Add your name on the photograph. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 52 DBE/PAT 2019 NSC 5.1.6 Veroboard planning/PCB design Design a Veroboard OR PCB design for the circuit you are going to build. ONLY do one or the other; do NOT do both. Place your design below. Final Design – Veroboard Same size and placement of components Use an X to show breaks made on the track. Printed circuit-board planning Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 53 DBE/PAT 2019 NSC 5.2 Assessment of the Design and Make Phase: Part 1 Achieved  Mark NO. FACET DESCRIPTION Not achieved  Circuit Diagram 1. The circuit diagram was drawn using EGD equipment. 1 2. The circuit diagram was drawn using EGD equipment and 1 CAD/any electronic design software. 3. The circuit diagram was drawn using correct symbols. 1 4. The circuit diagram has all labels – R1, C1, Tr1, etc. 1 5. The circuit diagram has all component values –100 Ω, 1 220 μF, etc. 6. The circuit diagram has a name. 1 7. The circuit diagram has a frame and title block (EGD 1 approach). Component List 8. Labels correlate with circuit diagram. 1 9. Description and values correlate with circuit diagram. 1 10. Quantities are correct. 1 Description of Operation 11. Basic function of the circuit is described correctly. 1 12. All subcircuits in the circuit diagram and component list are 1 included in the description. 13. Purposes of subcircuits in the circuit diagram are described 1 correctly. 14. Learner used own interpretation and did not copy from 1 another source verbatim. 15. Sources are acknowledged. 1 Tools/Instrument List 16. The tools/instrument list has been completed. 1 17. The tools/instruments listed all have a purpose for being used. 1 Evidence of Prototyping on Breadboard 18. Unique, original photos of the prototyping are included. 1 19. Unique, original photos include the learner name. 1 20. Photos are clear and in focus: 1 All components are clearly identifiable. 21. Prototype is operational. No photo, no mark. 2 22. Video of working prototype is available as confirmation. 3 PCB Design 23. Board design is included in the PAT file. 1 24. Component overlay showing placement is included. 1 25. Components are labelled the same as in the circuit diagram. 1 26. The design is original and does not match any other learner's 1 design. 27. Board layout (tracks/current flow) is functional and matches 1 the original circuit diagram. Circuit Board Manufacturing 28. Circuit board is etched neatly according to the PCB design. 5 29. The PCB is tinned neatly. 1 30. The soldered PCB, solder side, is covered with a clear 1 protective coating (Plastik 70/clear lacquer). 31. Holes are drilled neatly and are aligned in the middle of the 1 pads on the PCB. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 54 DBE/PAT 2019 NSC 32. Mounting holes of the PCB are drilled symmetrically. 1 33. All burrs are removed. 1 34. The PCB is cut neatly/squarely and edges are filed neatly. 1 35. Axial and radial components are placed neatly and flush with 1 the board. 36. Component orientation are aligned between similar 1 components (e.g. the gold band of all resistors are placed on the same side). 37. Soldered components – leads are cut off, flush and neat on 2 the solder side. 38. More than 60% of the solder joints are shiny (not dry joints). 2 39. Wire insulation is stripped to the correct length (no extra 2 copper showing). 40. Wiring is long enough to allow for dismantling and inspection. 1 41. Wiring is wrapped neatly. 1 42. A power switch is included and fitted to the enclosure. 2 43. A fuse/protection is included and fitted correctly where 2 applicable. 44. Wiring entering/exiting the enclosure is provided with a 2 grommet/applicable fittings/sockets where applicable. 45. Batteries are mounted using a battery housing/mounting 1 bracket and battery clip (NO double-sided tape). 46. The project has a pilot light/LED installed in the enclosure 2 showing when the circuit is operational. (Switch is on – must go out when fuse is blown.) 47. The project is fully operational and commissioned/installed in 10 the enclosure. TOTAL (PART 1 = 70 marks) NOTE: In projects where facets 43 and 44 are not applicable, the projects should be marked out of 66 and the marks adjusted accordingly. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 55 DBE/PAT 2019 NSC 5.3 Design and Make: Part 2 (a) Enclosure design • Design an enclosure for your project. • NO FREEHAND DRAWINGS. • Draw using EGD equipment OR use a CAD program. • Draw in first-angle orthographic projection. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 56 DBE/PAT 2019 NSC (b) Manufacture the enclosure neatly according to your design. (c) Choose a name for your device. Write down the name of the device below. (d) Design a unique logo for your device below. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 57 DBE/PAT 2019 NSC 5.4 Assessment of the Design and Make Phase: Part 2 Achieved  Mark Not achieved  NO. FACET DESCRIPTION Enclosure Design 1. Enclosure design is included in first-angle orthographic 1 projection. 2. Drawn design includes a title box and page border. 1 3. Isometric drawing included additionally. 1 4. Dimensions are included. 1 5. The name of the device is written in the PAT document. 1 6. The logo design is in the PAT document. 1 Subtotal (6 marks max.) Enclosure Manufacturing 7. Enclosure matches the design. 1 – Dimensions and placement correlate. 8. Name of the device is on the enclosure. 1 9. The logo design is on the enclosure. 1 10. The logo design on the enclosure is durable and not 1 merely a paper pasted on the enclosure (painted/used decoupage/screen printed/sublimation printed). 11. The enclosure is manufactured from scratch. 4 Does NOT include: cardboard, paper, margarine container Does include: sheet metal, Perspex, Plexiglas, wood, glass and other raw materials, injection-moulded plastic boxes 12. Holes/Cut-outs in the enclosure are made with the 2 appropriate tools. 13. Specification plate with the learner's name, operating 1 voltage, fuse rating and additional information on the project. 14. Enclosure is neatly prepped, painted and aesthetically 2 pleasing. 15. The circuit board is mounted using appropriate methods 1 inside the enclosure. (NO double-sided tape, Prestik, glue, chewing gum, masking tape, etc.) Subtotal (14 marks max.) TOTAL (PART 2 = 20 marks) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 58 DBE/PAT 2019 NSC 6. PROJECTS 6.1 Practical Project 1: 5 Watt mini-amplifier (portable speaker) This micro-sized high quality amplifier was originally designed to replace amplifiers in car radios where the original ICs are no longer available. This does not limit the use to that application. Use your imagination: There are a million other uses. Always use an adequate heat sink. THE CIRCUIT The TDA 2002 or TDA 2003 is used in a very straightforward audio amplifier configuration and only a few precautions must be taken when using it. Firstly, because of the very high input impedance, the input connections must be screened cable and kept as short as possible to eliminate pickup of stray RF and other interference. Secondly, the fact that the PC board is so small limits the amount of decoupling capacitance (C5) that can be provided on the board. If the supply does not have at least a few hundred microfarads smoothing, then the amplifier could go into oscillation. That means you have to place an 1 000 mF 16 V capacitor over the supply voltage. TIPS ON CONSTRUCTION No problems should be experienced when assembling this amplifier. Just check for the polarity of the electrolytic capacitors and make sure that the soldering is done properly. Care must also be taken when connecting the power to the PC board. NOTE: IF THE POLARITY IS REVERSED, THE IC WILL BE DESTROYED. COMPONENT LIST R1 Can be replaced with a 100 K preset if required 1 R1 100 K ¼ W Resistor Brown Black Yellow Gold 1 R2 47 Ohm ¼ W Resistor Yellow Violet Black Gold 1 R3 220 Ohm ¼ W Resistor Red Red Brown Gold 1 R4 2,2 Ohm ¼ W Resistor Red Red Red Gold 1 R5 22 Ohm ¼ W Resistor Red Red Black Gold 1 C1 10 uF 16 V Electrolytic Radial capacitor 1 C2 33 PF Non-polarised Ceramic capacitor 1 C3 100 uF 16 V Electrolytic Radial capacitor 1 C4 47 nF Non-polarised Capacitor (473, 0,047 uF) 1 C5 10 uF 16 V Electrolytic Radial capacitor 1 C6 470 uF 16 V Electrolytic Radial capacitor 1 C7 100 nF Non-polarised Capacitor (104, 0,1uF) 1 IC1 TDA 2002 OR TDA 2003 Sound IC 1 PP3 9 V Battery clip 1 10 cm Mono-screened cable for Signal IN Connection 1 PCB EFK # 1002 1 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 59 DBE/PAT 2019 NSC TOOLS AND EQUIPMENT Oscilloscope (analogue/digital) Analogue/Digital trainer with dual power supply Multimeter Side cutters Wire-stripper Soldering iron Helping hands PCB etching tank or similar Solder sucker CIRCUIT DIAGRAM BATT +V + C5 10 µF 16 V C1 10 µF 16 V GND C6 Signal + 1 5 470 µF 16 V + 4 2 + - 3 TDA2002V GND R3 220 Ω C4 R2 47 nF 47 Ω R1 C2 C7 100 kΩ 33 pF 100 nF + LS1 + - C3 R4 R5 100 µF 16 V 2,2 Ω 22 Ω Signal GND BATT -V 5 WATT MINI AMPLIFIER GND [Supplied by RSE Electronics] OR Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 60 DBE/PAT 2019 NSC 6.2 Practical Project 2: Traffic light RESOURCES TOOLS/INSTRUMENTS MATERIALS • Oscilloscope (analogue/digital) • 100 kΩ resistor • Analogue/Digital trainer with dual power supply • 220 Ω resistor x 3 • Electronics multimeter • 22 kΩ resistor x 1 • Soldering iron • LED green x 1 • Helping hands • LED yellow x 1 • PCB etching tank or similar • LED red x 1 • Solder sucker • 1 µF capacitor x 2 • Wire-stripper • 10 µF capacitor x 1 • Side cutters • 470 kΩ variable resistor x 1 • IC NE555 • IC CD 4017 • 1N4007 diode x 6 • PCB 150 x 100 mm • Solder • PCB etching chemicals CIRCUIT DIAGRAM TRAFFIC LIGHT CIRCUIT 1mF 100K 1mF 8 4 16 7 470K NE 555 3 14 CD 4017 15 22K 6 2 1 5 6 9 11 10 1 2 3 4 7 10mF 220Ω 220Ω 220Ω GREEN YELLOW RED Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology 61 DBE/PAT 2019 NSC 7. CONCLUSION Upon completion of the practical assessment task learners should be able to demonstrate their understanding of the industry, enhance their knowledge, skills, values and reasoning abilities, as well as establish connections to life outside the classroom and address real-world challenges. Furthermore, the PAT develops learners' life skills and provides opportunities for learners to engage in their own learning. Copyright reserved