Electrical Technology PAT GR 12 2021 (Electronics) Eng

Downloaded from hlayiso.com ELECTRICAL TECHNOLOGY (ELECTRONICS) GUIDELINES FOR PRACTICAL ASSESSMENT TASKS GRADE 12 2021 These guidelines consist of 44 pages. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 2 DBE/PAT 2021 NSC TABLE OF CONTENTS PAGE 1. INTRODUCTION 3 2. TEACHER GUIDELINES 4 2.1 How to administer PATs 4 2.2 How to mark/assess the PATs 4 2.3 PAT Programme of Assessment (PAT PoA) 5 2.4 Moderation of PATs 6 2.5 Absence/Non-submission of tasks 6 2.6 Simulations 7 2.7 Projects 7 2.8 Working marks sheet 8 3. LEARNER GUIDELINES 9 3.1 PAT 2021 cover page 9 3.2 Instructions to learners 10 3.2 Declaration of Authenticity 10 4. SIMULATIONS 11 4.1 Simulation 1: RLC series circuit 11 4.2 Simulation 2A: JFET amplifier circuit 15 Facet sheet for simulation 2A: JFET amplifier circuit 18 Simulation 2B: Darlington pair current amplifier 19 Facet sheet for simulation 2B 21 4.3 Simulation 3A: Monostable multivibrator using 555 IC 22 Simulation 3B: Inverting op-amp using 741 IC 24 Simulation 3C: Differentiator circuit using a 741 op-amp 26 Facet sheet for simulation 3A, 3B and 3C 28 4.4 Simulation 4: Hartley oscillator 29 Facet sheet: Hartley Oscillator 32 5. SECTION B: DESIGN AND MAKE 33 5.1 Design and Make: Part 1 34 5.2 Assessment of the Design and Make phase: Part 1 37 5.3 Design and Make: Part 2 39 5.4 Assessment of the Design and Make phase: Part 2 40 6. PROJECTS 41 6.1 Practical Project 6.1: 5 Watt Mini-amplifier (portable speaker) 41 6.2 Practical Project 6.2 (Electronics): Dual voltage power supply 43 6.3 Practical Project 3: Electronic piano 44 7. CONCLUSION 44 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 3 DBE/PAT 2021 NSC 1. INTRODUCTION The 18 Curriculum and Assessment Policy Statements subjects which contain a practical component all include a practical assessment task (PAT). These subjects are:  AGRICULTURE: Agricultural Management Practices, Agricultural Technology  ARTS: Dance Studies, Design, Dramatic Arts, Music, Visual Arts  SCIENCES: Computer Applications Technology, Information Technology, Technical Sciences; Technical Mathematics  SERVICES: Consumer Studies, Hospitality Studies, Tourism  TECHNOLOGY: Civil Technology, Electrical Technology, Mechanical Technology and Engineering Graphics and Design A practical assessment task (PAT) mark is a compulsory component of the final promotion mark for all candidates offering subjects that have a practical component and counts 25% (100 marks) of the end-of-the-year examination mark. The PAT is implemented across the first three terms of the school year. This is broken down into different phases or a series of smaller activities that make up the PAT. The PAT allows for learners to be assessed on a regular basis during the school year and it also allows for the assessment of skills that cannot be assessed in a written format, e.g. test or examination. It is therefore important that schools ensure that all learners complete the practical assessment tasks within the stipulated period to ensure that learners are resulted at the end of the school year. The planning and execution of the PAT differs from subject to subject. Practical assessment tasks are designed to develop and demonstrate a learner's ability to integrate a variety of skills in order to solve a problem. The PAT also makes use of a technological process to inform the learner what steps needs to be followed to derive a solution for the problem. The PAT consists of four simulations and a practical project. The teacher may choose any ONE of the practical projects and any TWO simulations available for electronics. The teacher must apply assessment on an ongoing basis at the same time that the learner is developing the required skills. TWO simulations should be completed by the learners, in addition to the manufacturing of a practical project. The PAT incorporates all the skills the learner has developed throughout the year. The PAT ensures that all the different skills will be acquired by learners on completion of practical work, as well as the correct use of tools and instruments. Requirements for presentation A learner must present the following:  PAT file with all the evidence of simulations, design and prototyping. A copy of the PAT 2021 cover page. The relevant simulations and assessment sheets should be copied and handed to each learner to include in the file.  Practical project with: o Enclosure:  The file must include a design.  The enclosure and the design must match.  No cardboard boxes are allowed.  Plastic, wooden and metal enclosures are acceptable.  Enclosures that are manufactured and/or assembled by the learners are preferred.  The enclosure should be accessible for scrutiny inside.  Lids that are secured are preferred. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 4 DBE/PAT 2021 NSC o Circuit board:  The file should include the PCB design.  The PCB must be mounted inside the enclosure in such a manner that it can be removed for scrutiny. Alternatively, inspection can be made from the bottom in cases where translucent (see-through) enclosures are used.  Switches, potentiometers, connectors and other items must be mounted.  Wiring must be neat and bound/wrapped.  Wiring must be long enough to allow for the PCB to be removed and inspected with ease. o Logo and name:  The file should contain the logo and name design and specification plate.  Logo, specification plate and name must be prominent on the enclosure.  The logo/specification plate must be affixed in a permanent manner – painted, glued or stuck on with vinyl The PAT will have a financial impact on the school's budget and school management teams are required to make provision to accommodate this particular expense. PAT components and other items must be acquired timeously, for use by the learners, before the end of the first term at the start of the academic year. It is the responsibility of the HOD to ensure that the teacher is progressing with the PAT from the start of the school year. Provincial departments are responsible for setting up moderation timetables and consequently PATs should be completed in time for moderation. 2. TEACHER GUIDELINES 2.1 How to administer PATs Teachers must ensure that learners complete the simulations required for each term. The project should be started in January in order to ensure its completion by August. In instances where formal assessments take place, the teacher has to assume the responsibility thereof. The PAT should be completed during the FIRST THREE TERMS and must be ready at the start of PAT moderation. Teachers must make copies of the relevant simulations and hand them to learners at the beginning of each term. The PAT must not be allowed to leave the workshop and must be kept in a safe place at all times when learners are not working on them. The weightings of the PAT must be adhered to and teachers are not allowed to change weightings for the different sections. 2.2 How to mark/assess the PATs The PAT for Grade 12 will be set and assessed internally, but moderated externally. All formal assessment will be done by the teacher. The teacher is required to produce a working model and model answer file that sets the baseline for assessment at a Highly Competent Level for every project choice exercised by the learners. This file must include all the simulations with answers the teacher has done him/herself. The teacher will use the model answers and project to assess the simulations and projects of the learners. Once a facet sheet has been completed by the teacher, assessment will be deemed to be complete. No re-assessment will be done once the facet sheets have been completed and captured by the teacher. Learners must ensure that the work is done to the required standard before the teacher finally assesses the PAT during each stage of completion. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 5 DBE/PAT 2021 NSC 2.3 PAT Programme of Assessment (PAT PoA) The programme of assessment (PoA) of the PAT is as follows: TIME FRAME ACTIVITY RESPONSIBILITY Preparation for Teacher – Builds the models and works out the model answers for PAT 2021 the simulations for 2021. Identifies shortages in tools, equipment and consumable items for simulations that must be procured in 2021. SMT – Receives procurement requests from teachers and processes payments for the acquisition of required items January–March Simulation 1 Teacher – Copies and hands out simulations 2021 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday January 2021 PAT project – Teacher – Obtains quotations for PAT projects procurement Principal – Approves PAT procurement for PAT projects Teacher – Ensures that PAT projects are ordered and delivered HOD – Checks in on teacher to see if the process is adhered to February 2021 PAT project – Teacher – Ensures that there is secure storage for PAT projects learners Teacher – Hands out and takes in PAT projects commence with Teacher – Includes practical sessions for learners to complete the project PAT project every week Learners – Commence with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis April–June Simulation 2 Teacher – Copies and hands out simulations 2021 Learners – Complete simulations Teacher – Assesses simulations HOD – Checks if tasks have been completed and marked by the teacher before the holiday April–June Moderation of District subject facilitator/subject specialist will visit the school and 2021 Simulation 1 moderate simulation 1 10% of learners' work is moderated April–June PAT project – Teacher – Ensures that there is secure storage for PAT projects 2021 learners Teacher – Hands out and takes in PAT projects continue with Teacher – Includes practical sessions for learners to complete the project PAT project every week Learners – Continue with completion of the PAT project HOD – Checks in on teacher to ensure that practical workshop sessions take place on a weekly basis July holidays PAT Learners that are behind on the PAT are required to complete the 2021 intervention project during this holiday. July–August Moderation of District subject facilitator/subject specialist will visit the school and 2021 Simulation 2 moderate simulation 2 – different learners from the previous term 10% of learners' work is moderated July–August PAT project – Teacher – Ensures that there is secure storage for PAT projects 2021 completion Teacher – Hands out and takes in PAT projects Teacher – Completes the PAT project with learners and compiles the PAT file Learners – Complete the PAT project and file HOD – Checks to see that 100% of the PAT files and projects are completed and assessed September– PAT PAT projects are moderated by subject facilitators/subject October 2021 moderation specialists from the province and learners are available to demonstrate skills 10% of learners are moderated randomly Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 6 DBE/PAT 2021 NSC 2.4 Moderation of PATs Provincial moderation of each term's simulations will start as early as the following term. Simulation 1 should be moderated as soon as the second term starts. Similarly, Simulation 2 will be moderated in July. The project will, however, only be moderated on completion. During moderation of the PAT the learner's file and project must be presented to the moderator. The moderation process is as follows:  During moderation, learners are randomly selected to demonstrate the different simulations. Both simulations will be moderated.  The teacher is required to build an exemplar model for each project type chosen for the school.  This model must be on display during moderation.  The teacher's model forms the standard of the moderation at Level 4 (Highly Competent).  Level 5 assessments must exceed the model of the teacher in skill and finishing.  Learners who are moderated will have access to their files during moderation and may refer to the simulations they completed earlier in the year.  Learners may NOT ask assistance from other learners during moderation.  All projects and files must be on display for the moderator.  If a learner is unable to repeat the simulation or cannot produce a working circuit during moderation, marks will be deducted and circuits assessed as not being operational.  The moderator will randomly select no fewer than two projects (not simulations) and the learners involved will have to explain how the project was manufactured.  Where required, the moderator should be able to call on the learner to explain the function and principles of operation, and request the learner to exhibit the skills acquired through the simulations for moderation purposes.  On completion the moderator will, if needed, adjust the marks of the group upwards or downwards, depending on the outcome of moderation.  Normal examination protocols for appeals will be adhered to, if a dispute arises from adjustments made. 2.5 Absence/Non-submission of Tasks The absence of a PAT mark in Electrical Technology without a valid reason: The learner will be given three weeks before the commencement of the final end-of-year examination to submit outstanding task. Should the learner fail to fulfil the outstanding PAT requirement, such a learner will be awarded a zero (0) for that PAT component. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 7 DBE/PAT 2021 NSC 2.6 Simulations Simulations are circuits, experiments and tests/tasks which the learner will have to build, test and measure and practically do as part of the development of practical skills. These skills have to be illustrated to the external moderator that visits the school at intervals during the school year. Teachers who make use of simulation programs on a computer may use it for the learners to practice on. However, it is required that the circuit be built using real components and that measurements be made with actual instruments for the purposes of assessment and moderation. The correct procedure for completing simulations is outlined below for teachers and school management teams who are responsible for the implementation of the PAT in Electrical Technology. STEP 1: The teacher will choose simulations from the provided examples. STEP 2: Compile a list of the components needed for every simulation. Add extra components as these items are very small and you will need extras, as these items are lost/damaged very easily when learners work with them. STEP 3: Contact three different electronics component suppliers for comparative quotations. STEP 4: Submit the quotations to the SMT for approval and procurement of the items. STEP 5: Place the components in storage. Collate items for each simulation, thus making it easier to distribute and use during practical sessions. Ensure that different values of components do not mix, as this would lead to components being used incorrectly and this could damage the component and in extreme cases, the equipment used. STEP 6: Copy the relevant simulations and hand them out to learners at the start of the term. Teachers are allowed to adjust circuits and component values to suit their environment/ resource availability. Teachers are required to develop a set of model answers in the teacher's file. Moderators will use the teacher's model answers and artefacts when moderating. 2.7 Projects The projects are construction projects teachers can choose for their learners. These projects are based on proven circuits provided from schools and subject advisors. The projects are based on working prototypes and require careful construction in order for it to operate correctly. Projects are varied in cost and teachers must ensure that the projects chosen fall within the scope of the school's budget. Once the teacher has decided on a circuit, he/she must construct the prototype. Thereafter, copies of the provided circuit can be made and distributed to learners. They MUST redraw these circuits in their file correctly. The description of the operation of the circuits is NOT complete. It is required of learners to interrogate the function of the components in the provided circuit. They should elaborate on the purpose of components in the circuit. It is recommended that those learners investigate similar circuits available on the internet and in the school library or workshop reference books. Copyright reserved Please turn over

Electrical Technology: Electronics Downloaded from hlayiso.com 8 DBE/PAT 2021 NSC 2.8 Working mark sheet (A working Excel file is provided with this PAT) PAT mark sheet Term 1 Term 2 Project Mark out of Moderated Simulation 1 Simulation 2 Design Design Total = Term 1 + and and Make Term 2 + Project 50 50 Make Part 2 100 Mark 250 Part 1 30 No. Name of Learner 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Total Average Teacher Name: Principal Name: Moderator Name: Signature: Signature: Signature: Date: Date:_______________________ Date:__________________ Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 9 DBE/PAT 2021 NSC 3. LEARNER GUIDELINES PAT 2021 cover page (Place this page at the front of the PAT.) Department of Basic Education Grade 12 CAPS for Technical High Schools Practical Assessment Task – Electrical Technology Time allowed: Terms 1–3 (2021) Learner Name: Class: School: Specialisation: ELECTRONICS Complete TWO simulations. Project (Write the name of the project): _____________________________ Evidence of moderation: NOTE: When the learner evidence (LE) selected has been moderated at school level, the table will contain evidence of moderation. Provincial moderators will sign the provincial moderation and only sign if re-moderation is needed. Moderation Signature Date Signature Date School-based Provincial moderation Re-moderation Mark allocation Moderated PAT Component Maximum Mark Learner Mark Mark Simulation 1 50 Simulation 2 50 Design and Make Project – Circuit 120 Design and Make Project – Enclosure 30 Total 250 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 10 DBE/PAT 2021 NSC 3.1 Instructions to learner  The practical assessment task counts 25% of your final promotion mark.  All work produced by you must be your own effort. Group work and co-operative work is not allowed.  The practical assessment task must be completed over three terms.  The PAT file must contain 2 simulations and a practical project.  Calculations should be clear and include units. Calculations should be rounded off to TWO digits. SI units should be used.  Circuit diagrams can be hand-drawn or drawn on CAD. NO photocopies or scanned files are allowed.  Photos are allowed and can be in colour or greyscale. Scanned photos and photocopies are allowed.  This document must be placed inside your PAT file together with the other evidence.  Learners with identical photos will be penalised and receive zero for that section 3.2 Declaration of Authenticity (COMPULSORY) Declaration: I herewith declare that the work represented in this evidence is entirely my own effort. I understand that if proven otherwise, my final results may be withheld. Signature of learner Date Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 11 DBE/PAT 2021 NSC 4. SIMULATIONS 4.1 Simulation 1: RLC series circuit Name of learner: Mark Class: Date Completed: _______ 50 Date Assessed: Assessor Signature: ______________ Date Moderated: Moderator Signature: ______________ 4.1.1 Purpose:  To understand the operation of a resistor, inductor and capacitor in a series circuit with an AC supply.  To understand resonant frequency.  To compare the measured and the calculated values. 4.1.2 Procedure: Build the series RLC circuit in FIGURE 4.1.4 on the breadboard using the components provided. Connect the circuit to a function generator. Set the output signal voltage of the function generator to 3 V peak to peak with a frequency of 1 kHz. 4.1.3 Required resources: COMPONENTS TOOLS AND EQUIPMENT R1 = 1 kΩ resistor Multimeter L1 = 1 µH inductor Function generator C1 = 1 µF capacitor Leads Breadboard Side cutters Pair of pliers Oscilloscope Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 12 DBE/PAT 2021 NSC 4.1.4 Circuit diagram: L1 R1 C1 VR VL VC It -1.5/1.5Volt 1 KHz Vt FIGURE 4.1.4: RLC CIRCUIT DIAGRAM 4.1.5 Complete TABLE 4.1.5 by entering values of VR, VL, VC, VT, and IT measured. NOTE: Alternatively measure with the oscilloscope and convert to Vrms values. METERS CONNECTED ACROSS MEASUREMENTS VR VL VC VT IT (5) TABLE 4.1.5 4.1.6 Calculate the following: (a) The inductive reactance of the inductor. (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 13 DBE/PAT 2021 NSC (b) The capacitive reactance of the capacitor (3) (c) The impedance of the circuit (3) (d) The total current in the circuit using calculated values. (3) (e) The voltage drop across the resistor using calculated values. (3) (f) The voltage drop across the inductor using calculated values. (3) (g) The voltage drop across the capacitor using calculated values. (3) (h) The resonant frequency for the circuit. (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 14 DBE/PAT 2021 NSC 4.1.7 Compare the measured values with the calculated values and enter the values in the table below: QUANTITIES MEASURED CALCULATED VALUES VALUES (a) Total current (b) Resistor voltage (c) Inductor voltage (d) Capacitor voltage (e) VXC at resonance (f) VXL at resonance Are the measured and calculated values the same? Yes or No. Motivate: (2) 4.1.8 Set the function generator to the resonant frequency and record the value of: (4) VXC = (V) VXL = (V) VR = (V) IT = (A) 4.1.9 Write a conclusion about the measurements observed in QUESTION 4.1.8 when the circuit is at resonance. (3) Subtotal: (38) LEVEL DESCRIPTOR MARKS OBTAINED 0 1 2 4 The candidate was The candidate was The candidate was able The candidate builded not able to build able to partially to correctly build the the circuit correctly the circuit on his build the circuit on circuit with the without the assistance own. his own. assistance of the of the teacher. teacher. The candidate was The candidate was The candidate The candidate not able to able to partially connected the connected the connect the connect the measuring instruments measuring instruments measuring measuring correctly and measured correctly and instruments. instruments to the the voltages and measured the voltages circuit. currents with the and currents on his assistance of the own. teacher. (12) Total: [50] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 15 DBE/PAT 2021 NSC 4.2 Simulation 2A: JFET amplifier circuit Name of learner: Mark Class: Date Completed: _______ 50 Date Assessed: Assessor Signature: ___________ Date Moderated: Moderator Signature: ______________ 4.2.1 Purpose: Build the JFET amplifier circuit in FIGURE 4.2.3 on a breadboard and investigate the advantage of using a Darlington pair compared to a single transistor. Display the input/output waveforms on an oscilloscope. 4.2.1 Required resources: TOOLS/INSTRUMENTS MATERIALS Analogue/Digital trainer 2 x 1 kΩ resistors Analogue/Digital oscilloscope 1 x 100  resistor Function generator 1 x 100 k resistor Variable DC power supply 1 x 2k2  resistor Side cutters 1 x 750  resistor Wire stripper 1 x 10 k resistor Multimeter 1 x 22 nF capacitor (223) 1 x 10 F electrolytic capacitor 32 V 1 x 2N5457 JFET (2N5459 or 2N3819) Connecting wires Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 16 DBE/PAT 2021 NSC 4.2.3 Procedure: (a) Build the circuit in FIGURE 4.2.3 on an experiment board. +9 V R4 2k2 Ω R1 1 kΩ C1 22 nF Function Generator 2N5457 R2 R6 Ch1 100 Ω 10 kΩ Ch2 R3 + C2 100 kΩ R5 10 µF 750 Ω d g 2N5457 g s s d FIGURE 4.2.3: JFET AMPLIFIER CIRCUIT (b) Connect the function generator across R1 and R2 and adjust it to provide a 1 V peak to peak sine wave. (If the output saturates, decrease the input voltage to obtain an undistorted output.) (c) Connect channel 1 of the oscilloscope across R2 and draw the waveform on the grid provided to scale. (d) Connect channel 2 of the oscilloscope across the output of the amplifier and draw the waveform on the grid provided to scale. V/Div:________ (Ch 1) V/Div:________ (Ch 2) T/Div: ___________ NOTE: 1 mark for each correctly drawn waveform and 1 mark for each correct oscilloscope setting. (5) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 17 DBE/PAT 2021 NSC (e) Make use of the oscilloscope settings and determine the peak value of the input and output signals. (3) VIN(peak) = ________________________ VOUT(peak) = ________________________ Phase shift between input and output? (Y/N): (f) Calculate the gain of the amplifier. (3) (g) Compare the two waveforms and write a conclusion regarding the circuit. (4) Simulation 2A: (15) Copyright reserved Please turn over

Electrical Technology: Electronics Downloaded from hlayiso.com 18 DBE/PAT 2021 NSC FACET SHEET OF SIMULATION 2A: JFET AMPLIFIER CIRCUIT MAXIMUM LEARNER FACET 1 FACET 2 FACET 3 FACET 4 POSSIBLE MARK MARKS Prepare for the Identify components Collect Collect instruments– Collect 4/4 = 1 simulation correctly (1) PSU/mini trainer (1) oscilloscope (1) hand tools (1) Hand tools Use side cutters Use wire stripper Use long-nose pliers 3/3 = 1 correctly (1) correctly (1) correctly (1) Preparation for Check the datasheet Set supply voltage Set input voltage 3 insertion of on the FET (1) correct at +9 V (1) correct at 1 V from components into function generator (1) breadboard. Correct connection Connect 6 nodes Polarity of JFET correct Polarity of C2 – correct 6/2 = 3 on breadboard – correctly (6/2 = 3) (2) (1) nodes and polarity Connection of Correct setting of the Correct setting of the Correct connection of 6/2 = 3 instruments function generator oscilloscope the oscilloscope (2) (2) (2) Circuit is working Output amplified Output phase vs. input 2 correct (1) phase (1) Housekeeping Cleaning the working Placing tools back in 2/2 = 1 area after the their places after work experiment (1) (1) Safety Observing safety before 2/2 = 1 being reminded (2) FACET sheet of Simulation 2A: 15 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 19 DBE/PAT 2021 NSC Simulation 2B: Darlington pair current amplifier 4.2.4 Resources TOOLS/INSTRUMENTS MATERIALS Analogue/Digital trainer 2 x BC 109 NPN transistors Analogue/Digital function generator 1 x LED Variable DC power supply 1 x 560 Ω resistor Side cutters 1 x 100 kΩ resistor Wire stripper Connecting wires 4.2.5 Procedure: (a) Construct the circuit in FIGURE 4.2.5 on an experiment board. FIGURE 4.2.5: TRANSISTOR CIRCUIT (b) Use your finger as a pathway for the current to connect points X and Y. Once your finger is connected, observe the brightness of the LED and record your findings. Connect an ammeter between the resistor and LED. (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 20 DBE/PAT 2021 NSC (c) Replace the single transistor with two identical BC109 transistors, as indicated in FIGURE 4.2.6. FIGURE 4.2.6: DARLINGTON PAIR (d) Connect points X and Y with your finger. Write down your observation of the brightness of the LED. Connect an ammeter between the resistor and LED. (2) (e) Compare the brightness of the LED when one transistor is used and when two transistors are used. Motivate why this happens. (2) (6) Copyright reserved Please turn over

Electrical Technology: Electronics Downloaded from hlayiso.com 21 DBE/PAT 2021 NSS FACET SHEET OF SIMULATION 2B: DARLINGTON PAIR CURRENT AMPLIFIER MAXIMUM LEARNER FACET 1 FACET 2 FACET 3 FACET 4 MARKS MARK Identify components Collect PSU/mini Collect Collect hand 4/2 = 2 Prepare for the correctly (1) trainer (1) instruments – tools (1) simulation multimeter (1) Use side cutters Use wire stripper 2/2 = 1 Hand tools correctly (1) correctly (1) Preparation for insertion Identify the pin layout of Set supply voltage 2/2=1 of components into the transistor correctly correctly at +9 V breadboard. (1) (1) Correct connection on Connect 6 nodes Polarity of TR1 and Polarity of LED – 6 breadboard – nodes and correctly (6/2 = 3) TR2 – correct (2) correct (1) polarity 1 transistor. 2 transistors 2 Circuit is working Brightness of LED – dim Brightness of LED – correct (1) bright (1) Cleaning the working Placing tools back in 2/2=1 Housekeeping area after the their places after work experiment (1) (1) Observing safety without 2/2=1 Safety being reminded (2) Facet sheet of Simulation 2B: [14] Simulation 2A: (15) Facet sheet of Simulation 2A: (15) Simulation 2B: (6) Facet sheet of Simulation 2B: (14) TOTAL SIMULATION 2: [50] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 22 DBE/PAT 2021 NSS 4.3 Simulation 3A: Monostable multivibrator using 555 IC Name of learner: Mark Class: Date Completed: _______ 50 Date Assessed: Assessor Signature: ______________ Date Moderated: Moderator Signature: ______________ 4.3.1 Purpose:  To build the monostable multivibrator in FIGURE in 4.3.3 using a 555 IC.  To justify the theory learned in class with the actual circuit. 4.3.2 Resources: TOOLS/INSTRUMENTS MATERIAL Experiment board 1 x 555 IC Voltmeter (multimeter) 2 x 10 kΩ resistors DC power supply 5 V 1 x 1 kΩ resistor Side cutters 2 x 470 Ω resistors Long-nose pliers 1 x 220 µF electrolytic capacitor 16 V Wire stripper 1 x 220 µF electrolytic capacitor 16 V 1 x LED 1 x push button/tactile switch Connecting wires 4.3.3 Procedure: Build the circuit diagram in FIGURE 4.3.3 on your experiment board. After the teacher has checked the circuit, switch the power ON. Connect a multimeter to measure the voltage on pin 2. Connect a multimeter to measure the voltage across C1. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 23 DBE/PAT 2021 NSS +5V R1 R2 10 kΩ 10 kΩ 8 4 7 Output 6 555 3 2 1 5 R4 Trigger 470 Ω V1 V C1 220 µF V2 V LED FIGURE 4.3.3: 555 MONOSTABLE MULTIVIBRATOR (a) Write down the voltage measured across pin 2. Voltage on pin 2 V1 = (1) (b) State the function of R1 with reference to pin 2 and the output. (2) (c) Press the trigger input and observe what happens to the voltage measurement across the capacitor. Write down the voltage measured across C1 just before the LED switches OFF (maximum charged voltage). Voltage across C1. V2 = (1) (d) Compare the voltage across C1 with the supply voltage. (2) (e) Press the trigger input twice within a short time frame to simulate switch bounce. Write down your observation. (3) (f) Replace capacitor C1 with a 100 µF capacitor. Switch ON the circuit, press the trigger input and observe. Write down you observation and give a reason why this happens. (3) Simulation 3A: (12) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 24 DBE/PAT 2021 NSS Simulation 3B: Inverting op-amp using 741 IC 4.3.4 Purpose: To build the inverting amplifier circuit in FIGURE 4.3.6 using a 741 op-amp and to display the output waveforms on an oscilloscope. Investigate the effect of the RF to RIN ratio on the gain and the output of the amplifier. 4.3.5 Required resources: TOOLS/INSTRUMENTS MATERIAL Function generator 1 x LM741 op-amp Dual trace oscilloscope 1 x 100 kΩ resistors +9 V 0 V -9 V DC power supply 1 x 50 k variable resistor Side cutters Connecting wires Wire stripper Calculator 4.3.6 Procedure:  Set the dual voltage power supply to +9 V/-9 V.  Set the function generator to deliver a 0,5 V peak 1 kHz sine wave.  Build the circuit in FIGURE 4.3.6 on your experiment board and connect it to the supply and input.  Connect channel 1 of the oscilloscope across the input to display at least TWO complete cycles.  Connect channel 2 of the oscilloscope across the output to display at least TWO complete cycles. (a) Build the circuit in FIGURE 4.3.6(a) on the experiment board with the variable resistor set to 10 kΩ. RF = 100 kΩ FG = 0,5 V 1 kHz RIN 50 kΩ +9 V VIN 2 _ 7 6 VOUT 3 CH1 + 4 CH2 -9 V VIN FG 10 kΩ 5 V / 1 kHz RIN = 50 kΩ 1 kΩ CH1 Alternative input connection FIGURE 4.3.6(a): 741 INVERTING OP-AMP Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 25 DBE/PAT 2021 NSS (b) Draw the input and output waveforms observed on the oscilloscope grid provided with the variable resistor set to 10 kΩ. V/Div:___________ (Ch 1) V/Div:___________ (Ch 2) T/Div: ___________ NOTE: 1 mark for each correctly drawn waveform. 1 mark for each correct oscilloscope setting. (5) (c) Use the oscilloscope settings to determine the values of: VIN = (1) VOUT = (1) (d) Calculate the gain of the amplifier using the determined voltage values. (3) (e) Set variable resistor RIN to the following values and record the output voltage in TABLE 4.3.6(e). (4) RIN OUTPUT VOLTAGE 47 kΩ 22 kΩ 4,7 kΩ 1 kΩ TABLE 4.3.6(e) (f) Compare the output voltages in TABLE 4.3.6(e) to the input voltage in (c) and write a conclusion. (3) Simulation 3B: (17) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 26 DBE/PAT 2021 NSS Simulation 3C: Differentiator circuit using a 741 op-amp 4.3.7 Purpose: Wire the differentiator op-amp circuit In FIGURE 4.3.9 using a 741 IC and display the output waveforms on an oscilloscope. Investigate how the value of RF and CIN affects the shape of the output signal. 4.3.8 Required resources: TOOLS/INSTRUMENTS MATERIALS Function generator 1 x 1 M resistor Dual trace oscilloscope 1 x 100 k resistor +9 V 0 -9 V DC power supply 1 x 47 k resistor Side cutters 1 x 22 k resistor Wire stripper (The feedback resistors can be replaced by a variable resistor within the prescribed range) 1 x 100 nF ceramic capacitor (104) 1 x LM 741 IC Connecting wires Alternatively a (102) or (103) ceramic capacitor may be used. Adjust the frequency accordingly. 4.3.9 Procedure:  Set the dual voltage power supply to +9 V/-9 V.  Set the function generator to deliver a 0,5 V peak 500 Hz triangular wave.  Wire the circuit in FIGURE 4.3.9 on your experiment board and connect it to the supply and input.  Connect channel 1 of the oscilloscope across the input to display at least TWO full cycles.  Connect channel 2 of the oscilloscope across the output to display at least TWO full cycles.  Vary RF to 100 kΩ, 47 kΩ and 22 kΩ, measure and record the output. (a) Wire the circuit in FIGURE 4.3.9 on the breadboard 1 MΩ +V FG 5 to 9 V 0,5 V / 500 Hz 100 nF VOUT CH 1 CH 2 -V 5 to 9 V FIGURE 4.3.9: DIFFERENTIATOR CIRCUIT USING A 741 OP-AMP Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 27 DBE/PAT 2021 NSS (b) Draw the input and output waveforms on the oscilloscope grid provided. V/Div:___________ (Ch 1) V/Div:___________ (Ch 2) T/Div: ___________ NOTE: 1 mark for each correctly drawn waveform. 1 mark for each correct oscilloscope setting. (5) (c) Adjust the 1 M resistor (RF) to 100 k. Switch on and observe. (d) Adjust the 100 k resistor (RF) to 47 k. Switch on and observe. (e) Adjust the 47 k resistor (RF) to 22 k. Switch on and observe. 4.3.10 CONCLUSION: Explain the effect different values of RF and CIN have on the output of the circuit. (2) Simulation 3C: (7) Copyright reserved Please turn over

Electrical Technology: Electronics Downloaded from hlayiso.com 28 DBE/PAT 2021 NSS FACET SHEET FOR SIMULATIONS 3A, 3B AND 3C MAXIMUM LEARNER FACET 1 FACET 2 FACET 3 FACET 4 POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/mini Collect instruments – Collect hand tools 4/2 = 2 simulation correctly (1) trainer (1) multimeter (1) (1) Hand tools Use side cutters Use long-nose pliers Use wire stripper 3/3 = 1 correctly (1) correctly (1) correctly (1) Preparation for Check the pinout of Set supply voltage Check the pinout of Set supply voltage 4/2 = 2 insertion of the 555 IC (1) correctly at +5V the 741 IC (1) correctly at +9 V 0 V components into for 555 IC (1) -9 V for 741 IC (1) breadboard. Correct connection Correct connection Correct connection Correct connection of Correct connection of 6/2 = 3 on breadboard – of 555 IC to supply of 555 IC to input 741 IC to supply 741 IC to input and nodes and polarity (1) and output (2) (1) output (2) Circuit is working S1 is pressed - LED stays on in Vout is inverted with Vout is an inverted 4 correctly LED 1(red) ON relation with the RIN= 10 kΩ (1) square wave when (1) RC time constant RF= 1 MΩ and CIN = (1) 100 nF (1) Housekeeping Cleaning the Placing tools back in 2/2 = 1 working area after places after work the experiment (1) (1) Safety Observing safety without being reminded 1 (1) Facet sheet for simulations 3A, 3B and 3C: [14] Simulation 3A: (12) Simulation 3B: (17) Simulation 3C: (7) Facet sheet 4: 741 of Simulation 3A, 3B and 3C: (14) TOTAL Simulation 3: [50] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 29 DBE/PAT 2021 NSS 4.4 Simulation 4: Hartley oscillator Name of learner: Mark Class: Date completed: 50 Date Assessed: Assessor Signature: Date Moderated: Moderator Signature: 4.4.1 Purpose: Construction of the Hartley oscillator circuit using discreet components and displaying the input/output waveforms on the oscilloscope. 4.4.2 Required resources: TOOLS/INSTRUMENTS MATERIALS Analogue/Digital trainer 1 x 2N2905 transistor Analogue/Digital oscilloscope 1 x 470 KΩ resistor Function generator 1 x 680 Ω resistor Multimeter 1 x 2,2 KΩ resistor Variable DC power supply 2 x 0,1 µF capacitor Side cutters 1 x 47 µF capacitor Wire stripper 1 x 0,1 µF capacitor Long-nose pliers 2 x 47 nF capacitor Connecting wire 1 x 0,47 µF capacitor 1 x 10 mH inductor 12 V DC supply 4.4.3 Procedure: (a) Build the circuit in FIGURE 4.4.3 on the breadboard. S1 12V R1=470KΩ RC=2.2KΩ Output C3=47nF PNP2N22905 2n2905 C2=0.1µF R2=1.5 KΩ L1=10mH C1= 0,1µF C4=0.47µF L2=10mH FIGURE 4.4.3: HARTLEY OSCILLATOR Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 30 DBE/PAT 2021 NSS Alternative circuit R1 RC S1 100 kΩ 1 kΩ C4 100 pF C2 Output 100 pF Q1 BC 547 9V R3 5 kΩ R2 C3 10 kΩ 100 nF L1 L2 10 mH 20 mH C1 10 pF (b) Switch ON the circuit. Draw the output of the oscillator on the grid provided. V/Div:___________ (Ch 1) T/Div: ___________ NOTE: 1 mark for a correctly drawn waveform. 1 mark for each correct oscilloscope setting. (3) (c) Measure and record the following DC voltages: VR1 = (2) VR2 = (2) VBE = (2) VCE = (2) VRC = (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 31 DBE/PAT 2021 NSS (d) Connect the oscilloscope, measure and record the resonant frequency ____________________kHz. (2) (e) Calculate the theoretical resonant frequency. (3) (f) Replace capacitors C1 and C2 with C1= 470 pF and C2 = 1 000 pF respectively. Measure and record the oscillation frequency: (2) (g) Calculate the theoretical resonant frequency of the new tank circuit. (3) (h) Short out capacitor C4, observe and record the AC and DC measurements at the collector and record them. AC = (V) (2) DC = (V) (2) (i) Explain the function of RC in the circuit (3) [30] Copyright reserved Please turn over

Electrical Technology: Electronics Downloaded from hlayiso.com 32 DBE/PAT 2021 NSS FACET SHEET FOR SIMULATION 4: HARTLEY OSCILLATOR MAXIMUM LEARNER FACET 1 FACET 2 FACET 3 FACET 4 POSSIBLE MARK MARKS Prepare for the Identify components Collect PSU/mini Collect instruments Collect hand tools 4 simulation correctly (1) trainer (1) – multimeter (1) (1) Hand tools Use side cutters Use long-nose pliers Use wire stripper 3 correctly (1) correctly (1) correctly (1) Preparation for insertion Refer to datasheet Set supply voltage 2 of components into for pinout (1) correctly at 12 V breadboard (1) Correct connection on Correct connection Correct polarity of Voltage 6 breadboard – nodes and of transistor (2) supply (1) measurement polarity across components (3) Circuit is working Oscillation 2 correctly frequency at output sine wave (2) Housekeeping Cleaning the Placing tools back in 2 working area after the places after the experiment (1) work (1) Safety Observing safety 1 without being reminded (1) Facet sheet of Simulation 4: [20] Subtotal Simulation 4: (30) Subtotal Facet sheet 4: (20) TOTAL Simulation 4: [50] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 33 DBE/PAT 2021 NSC 5. SECTION B – DESIGN AND MAKE Design and Make Project Time: January to August 2021 Learner Name: School: Class: Title/Type of Project: _____ INSTRUCTIONS  This section is COMPULSORY for all learners.  The teacher will choose a circuit for the project.  Any project constructed must include at least (but is not limited to): o SEVEN components o A variety of components (both active and passive) o PCB-making in some form o Soldering o An enclosure with a switch and protection  The checklist below must be used to ensure that all the required tasks for the PAT have been completed. PAT CHECKLIST NOTE: The learner MUST complete this checklist for the teacher BEFORE marking of that section takes place. NO. DESCRIPTION TICK () NO YES Design and Make: Part 1 1. Circuit diagram drawn   2. Circuit description filled in   3. Component list completed   4. Tools list for circuitry populated   5. Measuring instrument list filled in   6. Evidence of prototyping printed and pasted into the file   7. Learner's own Veroboard/PCB planning/design printed and included in file   Design and Make: Part 2 1. Enclosure design completed and included in the file   2. Unique name written down and on the enclosure   3. Logo designed and placed on the enclosure   Miscellaneous 1. Enclosure included in the project   2. Enclosure prepared and drilled according to the design   3. Enclosure finished off and completed with name and logo   4. PCB securely mounted in the enclosure using acceptable techniques   5. Circuit inside the enclosure is accessible   6. Internal wiring neat and ready for inspection   7. File and project completed and ready for moderation at the workshop/room   Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 34 DBE/PAT 2021 NSC 5.1 Design and Make: Part 1 5.1.1 Circuit diagram Draw a circuit diagram of your project and add it on the next page. 5.1.2 Project: Description of operation Use the space below to provide an overview of how the project functions. Use your own words and do some research of your own. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 35 DBE/PAT 2021 NSC 5.1.3 Component list List the components needed for the circuit diagram. LABEL DESCRIPTION AND VALUE QUANTITY 5.1.4 Tools/Instrument list List the tools needed to complete the project. DESCRIPTION PURPOSE/USE 5.1.5 Evidence of prototyping Take photographs of the working prototype on the breadboard using a digital camera or cellphone and insert here. Add your name on the photograph. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 36 DBE/PAT 2021 NSC 5.1.6 PCB design Design a printed circuit board layout for the circuit you are building. Print it out and insert here. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 37 DBE/PAT 2021 NSC 5.2 Assessment of the Design and Make Phase: Part 1 NO. FACET DESCRIPTION Mark Achieved = 1 Not achieved =  Circuit Diagram (10) 1. The circuit diagram was drawn using EGD equipment. 1 2. The circuit diagram was drawn using CAD/any electronic 1 design software. 3. The circuit diagram was drawn using correct symbols. 2 4. The circuit diagram has all labels – R1, C1, Tr1, etc. 2 5. The circuit diagram has all component values –100 Ω, 2 220 μF, etc. 6. The circuit diagram has a name/title. 1 7. The circuit diagram has a frame and title block. 1 (EGD approach). Component List (3) 8. Labels correlate with circuit diagram. 1 9. Description and values correlate with circuit diagram. 1 10. Quantities are correct. 1 Description of Operation (10) 11. Basic function of the circuit is described correctly. 2 12. All subcircuits in the circuit diagram and component list are 3 included in the description. 13. Purposes of subcircuits in the circuit diagram are described 3 correctly. 14. Learner used own interpretation and did not copy from 1 another source verbatim. 15. Sources are acknowledged. 1 Tools/Instrument List (2) 16. The tools/instrument list has been completed. 1 17. The tools/instruments listed all have a purpose for being used. 1 Evidence of Prototyping on Breadboard (10) 18. Unique, original photos of the prototyping are included. 1 19. Unique, original photos include the learner name. 2 20. Photos are clear and in focus: 2 All components are clearly identifiable. 21. Prototype is operational. No photo, no mark. 5 PCB Design (15) (If a kit is used in this section = 0) 22. Printed Circuit Board design is included in the PAT file. 1 23. PCB design is made using a CAD approach. 5 24. Component overlay showing placement is included. 1 25. Components are labelled the same as in the circuit diagram. 1 26. The design is original and does not match any other learner's 2 design. 27. Board layout (tracks/current flow) is functional and matches 5 the original circuit diagram. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 38 DBE/PAT 2021 NSC NO. FACET DESCRIPTION Mark Achieved = 1 Not achieved =  Circuit Board Manufacturing (70) 28. Circuit board is etched neatly according to the PCB design. 10* 29. The learner's name is etched onto the circuit design. 2 30. Holes are drilled neatly and are aligned in the middle of the 2 pads on the PCB. 31. Mounting holes of the PCB are drilled symmetrically. 2 32. All burrs are removed. 2 33. The PCB is cut neatly/squarely and edges are filed neatly. 2 34. Axial and radial components are placed neatly and flush with 2 the board. 35. Component orientation is aligned between similar 2 components (e.g. the gold band of all resistors are placed on the same side). 36. Soldered components – leads are cut off, flush and neat on 3 the solder side. 37. More than 60% of the solder joints are shiny (not dry joints). 5 38. Wire insulation is stripped to the correct length (no extra 3 copper showing). 39. Wiring is long enough to allow for dismantling and inspection. 2 40. Wiring is wrapped neatly. 2 41. A power switch is included and fitted to the enclosure. 2 42. A fuse/Protection is included and fitted correctly 2 where applicable. 43. Wiring entering/exiting the enclosure is provided with a 2 grommet/applicable fittings/sockets where applicable. 44. Batteries are mounted using a battery housing/mounting 2 bracket and battery clip (NO double-sided tape). 45. The project has a pilot light/LED installed in the enclosure 3 showing when the circuit is operational. (Switch is on – must go out when fuse is blown.) 46. The project is fully operational and commissioned/installed in 20 the enclosure. TOTAL (PART 1 = 120 marks) NOTE: In projects where facets are not applicable, the projects should be marked and the totals adjusted accordingly. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 39 DBE/PAT 2021 NSC 5.3 Design and Make: Part 2 5.3.1 Enclosure design  Design an enclosure for your project.  NO FREEHAND DRAWINGS.  Draw using EGD equipment OR use a CAD program.  Draw in first-angle orthographic projection.  Add your drawings after this page.  Use colour to enhance your drawing. 5.3.2 Manufacture the enclosure neatly according to your design. You may use pre-cut panels from metal, wood and/or Perspex/Plexiglass. You must, however, construct/assemble these parts. Injection moulded enclosures are also acceptable. It is important that your enclosure and the placement of the parts align with your design. 5.3.3 Choose a name for your device. Write down the name of the device below. 5.3.4 Design a unique logo for your device, as well as a specification plate and attach it after this page. [30] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 40 DBE/PAT 2021 NSC 5.4 Assessment of the Design-and-Make-Phase: Part 2 NO. FACET DESCRIPTION Mark Achieved = 1 Not achieved =  Enclosure Design (10) 1. Enclosure design is included in first-angle orthographic projection. 2 2. Drawn design includes a title box and page border. 1 3. Isometric drawing included additionally. 2 4. Dimensions are included. 2 5. The name of the device is written in the PAT document. 1 6. The logo design and specification plate design is in the 2 PAT document. Subtotal (10 marks max.) Enclosure Manufacturing (20) 7. Enclosure matches the design. 1 – Dimensions and placement correlate. 8. Name of the device is attached on the enclosure. 1 9. The logo design is attached on the enclosure. 2 10. The logo design on the enclosure is durable and not merely a paper pasted on the enclosure (painted/used decoupage/screen 2 printed/sublimation printed). 11. The enclosure is manufactured from scratch/pre-cut parts. Does NOT include: cardboard, paper, margarine container 5 Does include: sheet metal, Perspex, Plexiglas, wood, glass and other raw materials, injection-moulded plastic boxes 12. Holes/Cut-outs in the enclosure are made with the appropriate 3 tools. 13. Specification plate with the learner's name, operating voltage, fuse rating and additional information on the project. 2 14. Enclosure is neatly prepared, painted and aesthetically pleasing. 2 15. The circuit board is mounted using appropriate methods inside the enclosure. (NO double-sided tape, Prestik, glue, chewing gum, 2 masking tape, etc.) Subtotal (20 marks max.) TOTAL (PART 2 = 30 marks) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 41 DBE/PAT 2021 NSC 6. PROJECTS Practical Project 6.1: 5-watt mini amplifier (portable speaker) This micro-sized high-quality amplifier was originally designed to replace amplifiers in car radios where the original IC is no longer available. This does not limit the use to that application: use your imagination; there are a million other uses. Always use an adequate heat sink. THE CIRCUIT The TDA 2002 or TDA 2003 is used in a very straightforward audio amplifier configuration and only a few precautions must be taken when using it. Firstly, because of the very high input impedance, the input connections must be screened cables and kept as short as possible to eliminate pickup of stray radio frequency and other interference. Secondly, the fact that the PC board is so small, limits the amount of decoupling capacitance (C5) that can be provided on the board. If the supply does not have at least a few hundred microfarads smoothing, then the amplifier could go into oscillation, and that means you have to place , say 1 000 µF 16 V capacitor over the supply voltage Tips on construction No problems should be experienced when assembling this amplifier. Just check for the polarity of the electrolytic capacitors and make sure that the soldering is done properly. Care must also be taken when connecting the power to the PC board. IF THE POLARITY IS REVERSED, THE IC WILL BE DESTROYED! COMPONENT LIST R1 Can be replaced with a 100 K pre-set if required R1 100 K 1/4 W resistor Brown Black Yellow Gold 1 R2 47 ohm 1/4 W resistor Yellow Violet Black Gold 1 R3 220 ohm 1/4 W resistor Red Red Brown Gold 1 R4 2,2 ohm 1/4 W resistor Red Red Gold 1 R5 22 ohm 1/4 W resistor Red Red Black Gold 1 C1 10 uF 16 V electrolytic radial capacitor 1 C2 33 pF non-polarized ceramic capacitor 1 C3 100 uF 16 V electrolytic radial capacitor 1 C4 47 nF non-polarized capacitor (473, 0,047 uF) 1 C5 10 uF 16 V electrolytic radial capacitor 1 C6 470 uF 16 V electrolytic radial capacitor 1 C7 100 nF non-polarized capacitor (104, 0,1 uF) 1 IC1 TDA 2002 OR TDA 2003 sound IC 1 PP3 9 V battery clip 1 10 cm mono-screened cable for signal IN connection 1 PCB EFK # 1002 1 Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 42 DBE/PAT 2021 NSC Required resources: TOOLS/INSTRUMENTS MATERIALS Oscilloscope (analogue/digital) Side cutters Analogue/Digital trainer with dual power supply Wire strippers Multimeter Soldering iron PCB etching tank or similar Helping hands Solder sucker Circuit Diagram BATT +V + C5 10 µF 16 V C1 10 µF 16 V GND C6 Signal + 1 5 470 µF 16 V + 4 2 + - 3 TDA2002V GND R3 220 Ω C4 R2 47 nF 47 Ω R1 C2 C7 100 kΩ 33 pF 100 nF + LS1 + - C3 R4 R5 100 µF 16 V 2,2 Ω 22 Ω Signal GND BATT -V 5 WATT MINI AMPLIFIER GND Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 43 DBE/PAT 2021 NSC Practical Project 6.2: (Electronics): Dual voltage power supply This project uses a centre-tapped transformer. The recommended rating of the transformer is 240 V to 18-0-18 V. NOTE: Sometimes the transformer you purchase outputs more than the specified value, so be careful while choosing the transformer. Capacitors C1 and C2 act as the smoothing capacitor; this is to even out any fluctuation in voltage. You can also add a bypass capacitor after the C1 and C2 to remove any AC noise which is not shown in the circuit. Besides the two voltage regulators, the 7812 gives positive 12 V and 7912 gives you negative 12 V. Other variants of voltage regulator ICs can also be used. NOTE: 78xx gives the positive output and 79xx gives the negative output. Capacitors C3 and C4 are used as the bypass capacitor to remove the AC noise and give a pure and cleaner DC Signal. Required resources: TOOLS MATERIALS Multimeter 1 x transformer 240 to 15-0-15 volt 1 x 7812 voltage regulator IC Side cutters - 4 x 1n4001 1 x 7912 voltage regulator IC Wire strippers 2 x 2 200 uF/25 v 1x toggle switch Soldering iron 2 x 10 uF/25 v 1 x in-line fuse and holder Helping hands 1 x 3,3 kΩ 1 m mains supply cable PCB etching tank or 1 x red LED 1 x 3 pin plug similar 2 x heat sink 1 x PCB Solder sucker 2 x 3 pin terminal block Circuit diagram: Vi Vo LM7812 BR 1 S1 TR 1 1N4001 R1 + C1 3k3 Ω Gnd + C3 2200 µF 10 µF 230 V 25 V LED 25 V 50 Hz 1 +12 V 2 0 3 C2 C4 -12 V + + 2200 µF 10 µF 25 V Gnd 25 V LM7912 Vi Vo Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Electronics 44 DBE/PAT 2021 NSC Practical Project 6.3: Electronic piano The electronic piano uses an astable mode of a common 555 timer integrated circuit to produce a tone that drives the speaker (piezo buzzer). Each musical note has a specific frequency. The frequency produced by the 555 timer in astable mode relies on the values of capacitor (C1) and two resistances (R1 and a combination of R2 to R9). The resistance of R2 to R9 will vary depending on which push button is pressed. R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 1,5 kΩ 1,3 kΩ 620 Ω 1 kΩ 1 kΩ 910 Ω 390 Ω 6,2 kΩ 1N 4001 1 kΩ +9V R10 S8 S7 S6 S5 S4 S3 S2 S1 470 Ω 8 4 7 555 3 6 C2 2 + 1 5 10 µF C1 100 nF + (104) Speaker TOOL MATERIALS Multimeter 9 V battery and battery clip 470 Ω resistor Side cutters SPST switch LED red x 1 Long-nose plier Fuse and fuse holder 100 nF ceramic capacitor Wire strippers 1N 4001 diode (104) Soldering iron 1 kΩ resistor x 3 10 µF electrolytic capacitor Solder sucker 390 Ω resistor 16V Helping hands 910 Ω resistor IC NE555 PCB etching tank or similar 620 Ω resistor Speaker 8 Ω/buzzer 1k3 Ω resistor PCB 1k5 Ω resistor Solder Etching chemicals NOTE: All circuits MUST include an ON/OFF switch with a ON indicator and fuse protection. 7. CONCLUSION On completion of the practical assessment task learners should be able to demonstrate their understanding of the industry, enhance their knowledge, skills, values and reasoning abilities as well as establish connections to life outside the classroom and address real-world challenges. The PAT furthermore develops learners' life skills and provides opportunities for learners to engage in their own learning. Copyright reserved