Electrical Technology Nov 2023 (Digital) Eng_hlayiso.com_.pdf

Downloaded from hlayiso.com GRAAD 12 NATIONAL SENIOR CERTIFICATE GRADE 12 ELECTRICAL TECHNOLOGY: DIGITAL ELECTRONICS NOVEMBER 2023 MARKS: 200 TIME: 3 hours This question paper consists of 18 pages, a 1-page formula sheet and an 8-page answer sheet. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 2 DBE/November 2023 NSC INSTRUCTIONS AND INFORMATION 1. This question paper consists of SIX questions. 2. Answer ALL the questions. 3. Answer the following questions on the attached ANSWER SHEETS: QUESTIONS 3.2.5, 3.4.3, 3.5.3 and 3.7 QUESTIONS 5.2.2, 5.4, 5.5.1 and 5.5.2 QUESTIONS 6.5, 6.7 and 6.11 4. Write your centre number and examination number on every ANSWER SHEET and hand them in with your ANSWER BOOK, whether you have used them or not. 5. Sketches and diagrams must be large, neat and FULLY LABELLED. 6. Show ALL calculations and round off answers correctly to TWO decimal places. 7. Number the answers correctly according to the numbering system used in this question paper. 8. You may use a non-programmable calculator. 9. Calculations must include: 9.1 Formulae and manipulations where needed 9.2 Correct replacement of values 9.3 Correct answer and relevant units where applicable 10. A formula sheet is attached at the end of this question paper. 11. Write neatly and legibly. Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 3 DBE/November 2023 NSC QUESTION 1: MULTIPLE-CHOICE QUESTIONS Various options are provided as possible answers to the following questions. Choose the answer and write only the letter (A–D) next to the question numbers (1.1 to 1.15) in the ANSWER BOOK, e.g. 1.16 D. 1.1 The following can be considered as dangerous practices: A The use (or misuse) of power tools B The incorrect use and handling of hand tools C The etching of printed circuit boards. D All the above-mentioned. (1) 1.2 The … is a switching circuit with two inputs that is able to store one bit of data at a time. A bistable multivibrator B monostable multivibrator C astable multivibrator D passive integrator (1) 1.3 An op-amp application that uses positive feedback is the … A comparator. B summing amplifier. C Schmitt trigger. D differentiator. (1) 1.4 The op-amp comparator is an extremely sensitive circuit because … A it is the only op-amp application that uses closed loop gain. B there is no feedback connection between the output and the input. C it makes use of the virtual ground concept. D the supply voltage is connected to it. (1) 1.5 ONE of the key operating principles in an op-amp integrator circuit: A When a constant current is fed to the capacitor, it will charge at a constant fixed rate rather than exponentially. B The two input terminals of the op amp have different voltages at all times. C The inputs of the op amp draw maximum current so that any input current is blocked by the feedback circuit. D The current fed to the capacitor causes it to charge exponentially. (1) 1.6 A … circuit is used to eliminate switch bounce in switching circuits. A comparator B bistable multivibrator C monostable multivibrator D differentiator (1) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 4 DBE/November 2023 NSC 1.7 When negative feedback is used in an op amp, the bandwidth … A increases. B decreases. C is equal to zero. D stays the same. (1) 1.8 When light passes through a filter which allows only a single plane of light to pass through and blocks the other planes of light, it is known as … of light. A connection B unification C polarisation D combination (1) 1.9 A device that converts a binary code into a recognisable decimal form, either as a digit or a character, is called a/an … A encoder. B parallel adder. C decoder. D binary adder. (1) 1.10 A clocked JK flip-flop is in a toggle condition when … A J = 1, K = 1 B J = 1, K = 0 C J = 0, K = 1 D J = 0, K = 0 (1) 1.11 Logic circuits that rely on the flip-flop as its basic building element is known as … logic circuits. A combinational B sequential C incessant D consecutive (1) 1.12 A device that is free running, with its operation not relying on the additional input of an input clock pulse, is known as a/an … device. A latching B synchronous C gate D asynchronous (1) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 5 DBE/November 2023 NSC 1.13 The bus that is used mainly for the CPU to issue instructions to both memory and input/output ports is known as the … bus. A data B address C system D control (1) 1.14 The term 'SCI' stands for … A serial communication interface. B standard communication interface. C serial command interface. D standard command interface. (1) 1.15 Data communication where all data and information flows in only one direction from transmitter to receiver is known as … communication. A duplex B fundamental C simplex D rudimentary (1) [15] QUESTION 2: OCCUPATIONAL HEALTH AND SAFETY 2.1 Name TWO incidents arising out of activities of people at the workplace that must be reported to the health and safety inspector. (2) 2.2 Define the term danger with reference to the Occupational Health and Safety Act, 1993 (Act 85 of 1993). (2) 2.3 Explain why the location of the emergency master switch is important for safety in and around the workshop. (2) 2.4 State TWO effects a third-degree burn has on a person's body. (2) 2.5 Name TWO first-aid steps to take after a person has been shocked by an electric current. (2) [10] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 6 DBE/November 2023 NSC QUESTION 3: SWITCHING CIRCUITS 3.1 Differentiate between bistable multivibrators and astable multivibrators with reference to the output states. (2) 3.2 FIGURE 3.2 below shows the circuit of an op amp as a bistable multivibrator. Answer the questions that follow. +9V S1 C1 = 10 µF 2 7 R3 6 741 1 kΩ 3 4 R2 1 kΩ R5 1 kΩ V R4 680 Ω S2 R1 470 Ω -9V FIGURE 3.2: BISTABLE MULTIVIBRATOR 3.2.1 Explain the function of R1 and R2. (2) 3.2.2 State the polarity of the output when S2 is pressed. (1) 3.2.3 Explain the operation of the circuit when S1 is pressed. (1) 3.2.4 Deduce the value of the output voltage when S1 is pressed. (3) 3.2.5 Refer to the input in FIGURE 3.2.5 below and draw the output waveform on the ANSWER SHEET for QUESTION 3.2.5. Input 0V t FIGURE 3.2.5: INPUT PULSES (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 7 DBE/November 2023 NSC 3.3 Refer to FIGURE 3.3 below and answer the questions that follow. +6V R2 R1 100 kΩ 33 kΩ 8 4 7 Output 6 555 3 2 1 5 R3 Trigger 470 Ω C1 220 µF FIGURE 3.3: MONOSTABLE MULTIVIBRATOR 3.3.1 State whether this circuit uses an active high trigger or an active low trigger to set the output. (1) 3.3.2 Determine the threshold voltage of the circuit. (1) 3.3.3 Explain the operation of the circuit when the trigger is pressed. (5) 3.3.4 State how you would eliminate any unwanted noise from the supply that might affect the timing of the circuit. (2) 3.4 Refer to FIGURE 3.4 below and answer the questions that follow. +9V R1 10 k 8 4 7 R3 R2 1k 555 1k 3 2 6 1 5 LED C1 C2 10 µF 10 nF FIGURE 3.4: ASTABLE MULTIVIBRATOR Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 8 DBE/November 2023 NSC 3.4.1 Explain the term duty cycle with reference to multivibrator outputs. (2) 3.4.2 State whether the charging time of the capacitor or the discharging time of the capacitor is longer. Motivate your answer. (3) 3.4.3 Draw the voltage waveform that appears across capacitor C 1 for ONE full cycle on the answer sheet for QUESTION 3.4.3. (4) 3.5 FIGURE 3.5 below shows the circuit of an inverting Schmitt trigger. +9 V VOUT 5V R1 -9 V 6,8 kΩ R2 5 kΩ FIGURE 3.5: INVERTING SCHMITT TRIGGER 3.5.1 State the advantage of making R2 variable. (1) 3.5.2 Calculate the value of the trigger voltage if R2 is set to 2,2 kΩ. (3) 3.5.3 Draw ONE cycle of the input and output waveforms for the circuit on the ANSWER SHEET for QUESTION 3.5.3 when R2 is set to 2,2 kΩ and the input waveform is sinusoidal. (6) 3.5.4 State how the value of the trigger voltage can be decreased. (1) 3.6 Refer to FIGURE 3.6 below and answer the questions that follow. 0,5 V V1 C1 R1 5 kΩ RF 10 kΩ t C2 R2 5 kΩ +12 V 0,2 V V2 - t C3 R3 5 kΩ VOUT + 0,3 V V3 -12 V t FIGURE 3.6: INVERTING SUMMING AMPLIFIER Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 9 DBE/November 2023 NSC 3.6.1 State the purpose of the capacitors in series with the input resistors. (1) 3.6.2 Explain the advantage of using variable resistors instead of fixed- value resistors on the input of the amplifier. (2) 3.6.3 Calculate the output of the amplifier if all input resistors are set to 2 kΩ. (3) 3.7 FIGURE 3.7 below shows the op amp as differentiator with its input signal. Draw the output waveform on the ANSWER SHEET for QUESTION 3.7. RF CIN +V +V VIN - VOUT 0 + t -V -V 0V FIGURE 3.7: OP AMP AS DIFFERENTIATOR (3) [50] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 10 DBE/November 2023 NSC QUESTION 4: SEMICONDUCTOR DEVICES 4.1 Refer to FIGURE 4.1 below of an inverting operational amplifier and answer the questions that follow. R F = 1,2 kΩ RIN = 1 k Ω +15 V _ VOUT VIN = 60 mV + -15 V 0V FIGURE 4.1: INVERTING OPERATIONAL AMPLIFIER 4.1.1 State the purpose of the feedback resistor (RF). (1) 4.1.2 Explain why op amps are seldom used in open-loop mode. (2) 4.1.3 Calculate the voltage gain of the circuit. (3) 4.2 Refer to FIGURE 4.2 below and answer the questions that follow. C1 10 µF C2 +9 V 22 µF VIN VOUT RF RB -9 V 120 kΩ 10 kΩ R1 10 kΩ FIGURE 4.2: NON-INVERTING OP AMP 4.2.1 State TWO functions of resistor RB in FIGURE 4.2. (2) 4.2.2 Calculate the voltage gain of the circuit in FIGURE 4.2. (3) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 11 DBE/November 2023 NSC 4.3 Refer to FIGURE 4.3 below and answer the questions that follow. +Vcc Ground 1 8 Supply 5k Ω 5k Ω 5k Ω T Trigger 2 7 Discharge + _ + _ 2 1 R S Output 3 6 Threshold Flip- flop Output Q driver Control Reset 4 5 voltage FIGURE 4.3: 555 IC PIN LAYOUT 4.3.1 Name TWO applications of the 555 IC. (2) 4.3.2 State TWO disadvantages of the 555 IC. (2) 4.3.3 Describe the function of pin 4. (3) 4.3.4 State the functions of the following components in FIGURE 4.3 above: (a) NPN transistor (1) (b) Comparator 2 (1) [20] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 12 DBE/November 2023 NSC QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.1 Refer to the LED seven-segment display and answer the questions that follow. 5.1.1 Explain the difference between a common anode and a common cathode. (2) 5.1.2 State TWO methods that use transistors to connect the power supply to the seven-segment display. (2) 5.2 Refer to FIGURE 5.2 of a decimal-to-binary encoder below and answer the questions that follow. X & A & B Outputs & C & D 9 8 7 6 5 4 3 2 1 0 Y FIGURE 5.2: DECIMAL-TO-BINARY ENCODER 5.2.1 State the typical voltage levels at X and Y. (2) 5.2.2 Determine the binary code at the output when switch 9 is pressed. Write the answers on the ANSWER SHEET for QUESTION 5.2.2. (4) 5.3 Describe how a coherent picture is created on an LCD screen. (4) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 13 DBE/November 2023 NSC 5.4 Determine the sum produced by the three-bit parallel adder in FIGURE 5.4 below when the binary numbers 1112 and 1012 are added together, by completing boxes A to F on ANSWER SHEET 5.4. (HINT: A2 A1 A0 = 1112 and B2 B1 B0 = 1012 ) B2 A 2 B1 A1 B 0 A0 Ci Ci FA FA HA C0 C0 C0 Σ3 Σ2 Σ1 Σ0 FIGURE 5.4: THREE-BIT PARALLEL ADDER (6) 5.5 Refer to FIGURE 5.5 of the clocked RS-type flip-flop below and answer the questions that follow. S Q CLK R Q FIGURE 5.5: RS-TYPE FLIP-FLOP 5.5.1 Complete the logic circuit diagram of this flip-flop on ANSWER SHEET 5.5.1. (6) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 14 DBE/November 2023 NSC 5.5.2 Determine the output at Q by completing the timing diagrams on ANSWER SHEET 5.5.2. Assume that Q starts LOW. 1 2 3 4 Clock S R Q FIGURE 5.5.2 (4) 5.6 State the function of a decoder. (2) 5.7 Name ONE example of EACH of the following categories of flip-flops: 5.7.1 Asynchronous (1) 5.7.2 Synchronous (1) 5.8 Explain the following terms with reference to memory elements: 5.8.1 Negative edge triggering (2) 5.8.2 Propagation delay (2) 5.9 Briefly describe the following counters: 5.9.1 Full sequence counter (1) 5.9.2 Truncated counter (1) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 15 DBE/November 2023 NSC 5.10 Refer to FIGURE 5.10 of a counter below and answer the questions that follow. 1 Q0 Q1 Q2 LSB MSB Input J Q J Q J Q K Q K Q K Q FF0 FF1 FF2 Clock FIGURE 5.10 5.10.1 Identify the circuit in FIGURE 5.10. (1) 5.10.2 Explain how the counter will be enabled to count either up or down when the input is high. (6) 5.11 Refer to FIGURE 5.11 below and answer the questions that follow. C QA QB QC QD SET SET SET SET D Q D Q D Q D Q FFA FFB FFC FFD CLR Q CLR Q CLR Q CLR Q B A FIGURE 5.11 5.11.1 Identify the register in FIGURE 5.11. (1) 5.11.2 Label A, B and C. (3) 5.11.3 State ONE use of this register. (1) 5.11.4 Describe how data flows through the register. (3) [55] Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 16 DBE/November 2023 NSC QUESTION 6: MICROCONTROLLERS 6.1 Explain the term embedded memory in microcontrollers. (2) 6.2 Refer to the block diagram in FIGURE 6.2 below and answer the questions that follow. CPU RAM Address Value A MAR Address bus 0000 0101 0101 0001 0001 0110 DECODE UNIT 0010 0011 0111 ACC OP CODE OPERAND INSTRUCTION 0011 1001 0010 0000 0000 END 0001 ADDRESS ADD 0100 0000 0000 0010 ADDRESS SUBTRACT 0011 ADDRESS STORE B 0101 0011 0000 0101 ADDRESS LOAD 0110 0000 0001 0110 ADDRESS BRANCH ALWAYS 0111 0000 0000 BRANCH IF ACC 0111 ADDRESS =0 MDR 1000 0000 0000 1000 ADDRESS BRANCH IF ACC Data bus >= 0 1001 0000 0000 1001 0001 INPUT 1010 0000 0000 1001 0010 OUTPUT 1011 0000 0000 CIR 1100 0000 0000 1101 0000 0000 C CU 1110 0000 0000 Control bus 1111 0000 0000 FIGURE 6.2: DATA TRANSFER BLOCK DIAGRAM 6.2.1 Label A, B and C. (3) 6.2.2 State the function of the memory address register (MAR). (2) 6.2.3 State the function of the data bus. (2) 6.2.4 Explain the function of the random access memory (RAM). (2) 6.2.5 State why the RAM is said to be a volatile memory. (2) 6.3 Explain why an A/D converter is used with microcontrollers. (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 17 DBE/November 2023 NSC 6.4 Refer to communication protocol and answer the questions that follow. 6.4.1 Define communication protocol. (2) 6.4.2 State TWO types of communication protocols. (2) 6.5 The table below indicates the differences between SPI and I 2C communication peripherals. Complete TABLE 6.5 on the ANSWER SHEET for QUESTION 6.5. SPI I2C Half duplex Four-wire protocol Single master TABLE 6.5 (3) 6.6 Refer to FIGURE 6.6 below of an UART and answer the questions that follow. D0 D1 D2 A D3 D4 D5 RX D6 Parallel Serial TX D7 Parallel data in Serial data out R/W B CLK INT FIGURE 6.6 6.6.1 Label A and B. (2) 6.6.2 State how data is arranged in the UART protocol data flow. (4) 6.6.3 State TWO advantages of the UART. (2) Copyright reserved Please turn over

Downloaded from hlayiso.com Electrical Technology: Digital Electronics 18 DBE/November 2023 NSC 6.7 Complete TABLE 6.7 on the ANSWER SHEET for QUESTION 6.7 by comparing the characteristics of an RS-232 with that of an RS-485 communication protocol. CHARACTERISTICS RS-232 RS-485 Line configuration Single-ended Differential Maximum cable length 15 metres 1 200 metres Typical logic levels ±3 to ± 25 V Mode of operation TABLE 6.7 (3) 6.8 Explain the difference between an algorithm and a flowchart. (2) 6.9 State THREE important steps that can be followed to create a flow chart. (3) 6.10 Briefly explain why an I2C system requires the inclusion of pull-up resistors. (2) 6.11 FIGURE 6.11 on the ANSWER SHEET shows an incomplete flow chart of a PICAXE shopper access control system to adhere to Covid-19 protocols because of a new wave of infections.  This system will be set up at the entrance and exit of a fashion store. The entrance and exit are two separate doors.  This system will enable access control due to the Covid-19 pandemic.  It will consist of a red light and a green light.  Covid-19 protocols only allow a maximum of 25 shoppers at a time for this store.  The green light informs the shopper entering the fashion store that there are fewer than 25 shoppers inside.  The system will use two digital sensors.  Sensor 1 will increase the count when shoppers enter the fashion store.  Sensor 2 will decrease the count when shoppers exit the fashion store.  Sensor 1 will increase the count to 25 shoppers inside the fashion store and the program will toggle to the red light.  This will indicate a full fashion store.  Sensor 2 will reduce the count. The green light switches on if the count is less than 25, thus indicating that a shopper may enter the fashion store. Complete and label the flow chart of this device on the ANSWER SHEET for QUESTION 6.11. (10) [50] TOTAL: 200 Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC FORMULA SHEET SEMICONDUCTOR DEVICES VOUT  RF  RF Gain A V      OR AV  1 VIN  IN  R RIN  R  VOUT  VIN    F   R IN   R  VOUT  VIN  1  F   R IN  SWITCHING CIRCUITS  R R R  VOUT    V1 F  V2 F  ...VN F   R1 R2 RN  VOUT VOUT Gain A V   VIN V1  V2  ...VN  VOUT   (V1  V2  ...VN ) 2 AT 2 2 T T 2 FLOW CHART SYMBOLS Process Decision Terminator Data Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 3: SWITCHING CIRCUITS 3.2.5 Input 0V t +VSAT Output 0V Transfer mark to t answer book - VSAT MOD FIGURE 3.2.5 (3) 3.4.3 VC ⅔ VCC ⅓ VCC Transfer mark to answer book T MOD FIGURE 3.4.3 (4) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 3.5.3 (V) 9 VOUT 6 + VIN 3 Upper trigger 0 (t) Lower trigger -3 - VIN -6 Transfer mark to answer book -9 MOD FIGURE 3.5.3 (6) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 3.7 +V 0 -V +V 0 Transfer mark to answer book -V MOD FIGURE 3.7 (3) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 5: DIGITAL AND SEQUENTIAL DEVICES 5.2.2 X & A= & B= & C= & D= 9 8 7 6 5 4 3 2 1 0 Y Transfer mark to answer book MOD FIGURE 5.2 (4) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 5.4 B2 A 2 B1 A 1 B0 A 0 Ci Ci FA FA HA C0 C0 C0 Σ3 Σ2 Σ1 Σ0 D B F E C A Transfer mark to answer book MOD FIGURE 5.4 (6) 5.5.1 S Q CLK Q R Transfer mark to answer book MOD FIGURE 5.5.1 (6) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 5.5.2 1 2 3 4 Clock S R Q Transfer mark to answer book MOD FIGURE 5.5.2 (4) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET QUESTION 6: MICROCONTROLLERS 6.5 SPI I2C Half duplex Four-wire protocol Single master Transfer mark to answer book MOD TABLE 6.5 (3) 6.7 CHARACTERISTICS RS-232 RS-485 Line configuration Single-ended Differential Maximum cable length 15 metres 1 200 metres Typical logic levels ±3 to ± 25 V Mode of operation Transfer mark to answer book MOD TABLE 6.7 (3) Copyright reserved

Downloaded from hlayiso.com Electrical Technology: Digital Electronics DBE/November 2023 NSC CENTRE NUMBER: EXAMINATION NUMBER: ANSWER SHEET 6.11 Start No Leave store ? Yes Transfer mark to answer book MOD FIGURE 6.11 (10) Copyright reserved